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參數資料
| 型號： | 68HC05PL4B |
| 廠商： | Motorola, Inc. |
| 英文描述： | 8-Bit Microcontroller Units (MCU).(8位微控制器) |
| 中文描述： | 8位微控制器單元（MCU）。（8位微控制器） |
| 文件頁數： | 15/98頁 |
| 文件大小： | 1019K |
| 代理商： | 68HC05PL4B |
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April 30, 1998
GENERAL RELEASE SPECIFICATION
MC68HC05PL4
REV 2.0
GENERAL DESCRIPTION
MOTOROLA
1-5
triggering, the LED/IRQ pin requires an external resistor to VDD for “wired-OR”
operation. If the LED/IRQ is not used, it must be tied to the VDD supply. The
contains an internal Schmitt trigger as part of its input to improve noise immunity.
When this pin is LED, the LED bit in the MISCR controls the on/off function of the
connected LED. This LED pin sinks current via an internal pulldown resistor.
IRQEN — External Interrupt Request Enable
0 =
LED/IRQ pin configured as LED drive pin.
1 =
LED/IRQ pin configured as IRQ input pin, for external interrupts.
LED — LED Drive Output Control
1 =
Enable internal pulldown resistor, pin is logic low.
0 =
Disable internal pulldown resistor, pin is in high impedance state.
1.4.5 PA0, PA1/DTMF, PA2/TCAP, PA3/TCMP, PA4-PA6
These eight I/O lines comprise port A, a general purpose bidirectional I/O port.
The state of any pin is software programmable and all port B lines are configured
as inputs during power-on or reset.
PA0 is only available on MC68HC05PL4.
PA1 is shared with DTMF output of the DAC subsystem. This pin is configured as
an output pin for DTMF.
PA2 is shared with TCAP input of the 16-bit timer. This pin is configured as an
input pin for TCAP.
PA3 is shared with TCMP output of the 16-bit timer. This pin is configured as an
output pin for TCMP.
PA5 and PA6 have high current sinking capability; see Electrical Specifications
section for values.
1.4.6 PB0/KBI0-PB3/KBI3, PB4-PB7
These eight I/O lines comprise port B, a general purpose bidirectional I/O port.
The state of any pin is software programmable and all port B lines are configured
as inputs during power-on or reset.
All port B pins have internal pullups which can be individually enabled by software.
PB0-PB3 also have keyboard interrupt capability, which can be individually
enabled.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
MICSR
$001C
RESET
R
W
IRQEN
IRQS
TCMPEN
TCAPEN
LED
COPON
POR
0
0
0
0
0
0
0
0
Figure 1-5. Miscellaneous Control and Status Register (MICSR)
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