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參數(shù)資料
| 型號： | FM24C05ULVMT8 |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | I2C Serial EEPROM |
| 中文描述： | 512 X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8 |
| 封裝： | PLASTIC, TSSOP-8 |
| 文件頁數(shù)： | 10/14頁 |
| 文件大小： | 105K |
| 代理商： | FM24C05ULVMT8 |
10
www.fairchildsemi.com
FM24C04U/05U Rev. A.3
F
Acknowledge
The FM24C04U/05U device will always respond with an acknowl-
edge after recognition of a start condition and its slave address. If
both the device and a write operation have been selected, the
FM24C04U/05U will respond with an acknowledge after the
receipt of each subsequent eight bit byte.
In the read mode the FM24C04U/05U slave will transmit eight bits
of data, release the SDA line and monitor the line for an acknowl-
edge. If an acknowledge is detected, FM24C04U/05U will continue
to transmit data. If an acknowledge is not detected,FM24C04U/05U
will terminate further data transmissions and await the stop condi-
tion to return to the standby power mode.
Device Addressing
Following a start condition the master must output the address of
the slave it is accessing. The most significant four bits of the slave
address are those of the device type identifier. This is fixed as
1010 for all EEPROM devices.
Refer the following table for Slave Addresses string details:
Device
A0 A1 A2
Page
Blocks Addresses
Page Block
FM24C04U/05U
P
A
A
2
0, 1
A: Refers to a hardware configured Device Address pin.
P: Refers to an internal PAGE BLOCK.
All IIC EEPROMs use an internal protocol that defines a PAGE
BLOCK size of 2K bits (for Word addresses 0x00 through 0xFF).
Therefore, address bits A0, A1, or A2 (if designated 'P') are used
to access a PAGE BLOCK in conjunction with the Word address
used to access any individual data byte.
The last bit of the slave address defines whether a write or read
condition is requested by the master. A '1' indicates that a read
operation is to be executed, and a '0' initiates the write mode.
A simple review: After the FM24C04U/05U recognizes the start
condition, the devices interfaced to the IIC bus wait for a slave
address to be transmitted over the SDA line. If the transmitted
slave address matches an address of one of the devices, the
designated slave pulls the SDA line LOW with an acknowledge
signal and awaits further transmissions.
Device Type
Identifier
Device
Address
1
0
1
0
A2
A1
A0
R/W
(LSB)
24C04/05
Page
Block Address
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| FM24C05ULVN | I2C Serial EEPROM |
| FM24C05ULZEM8 | I2C Serial EEPROM |
| FM24C05ULZEMT8 | I2C Serial EEPROM |
| FM24C05ULZEN | CLIP -MK PCB SOCKET |
| FM24C05ULZM8 | I2C Serial EEPROM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FM24C05ULVN | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:I2C Serial EEPROM |
| FM24C05ULZ | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:4K-Bit Standard 2-Wire Bus Interface Serial EEPROM |
| FM24C05ULZEM8 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:I2C Serial EEPROM |
| FM24C05ULZEMT8 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:I2C Serial EEPROM |
| FM24C05ULZEN | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:I2C Serial EEPROM |
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