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參數(shù)資料
| 型號(hào)： | FM24C08UFN |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | I2C Serial EEPROM |
| 中文描述： | 1K X 8 I2C/2-WIRE SERIAL EEPROM, PDIP8 |
| 封裝： | DIP-8 |
| 文件頁(yè)數(shù)： | 6/14頁(yè) |
| 文件大小： | 105K |
| 代理商： | FM24C08UFN |
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www.fairchildsemi.com
FM24C08U/09U Rev. A.3
F
SDA
SCL
Master
Transmitter/
Receiver
Slave
Transmitter/
Receiver
Master
Transmitter
Slave
Receiver
Master
Transmitter/
Receiver
VCC
VCC
SDA
SCL
24C02/03
VCC
VCC
A0 A1 A2 VSS
24C02/03
A0 A1 A2 VSS
24C04/05
A1 A2 VSS
24C08/09
A2 VSS
VCC
To
VSS
To
VSS
To
VSS
VCC
VCC
VCC
To
VCC
To
VSS
To
VSS
To
VCC
To
VSS
To
VCC
Typical System Configuration
Note:
Due to open drain configuration of SDA and SCL, a bus-level pull-up resistor is called for, (typical value = 4.7k
)
Example of 16K of Memory on 2-Wire Bus
Note:
The SDA pull-up resistor is required due to the open-drain/open collector output of IIC bus devices.
The SCL pull-up resistor is recommended because of the normal SCL line inactive 'high' state.
It is recommended that the total line capacitance be less than 400pF
Device
Address Pins Present
A1
Memory Size
# of Page
Blocks
A0
A2
FM24C02U/03U
Yes
Yes
Yes
2048 Bits
1
FM24C04U/05U
No
Yes
Yes
4096 Bits
2
FM24C08U/09U
No
No
Yes
8192 Bits
4
FM24C16U/17U
No
No
No
16,384 Bits
8
SDA
SCL
STOP
CONDITION
START
CONDITION
WORD n
8th BIT
ACK
tWR
Write Cycle Timing
Note:
The write cycle time (t
WR
) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle.
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