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參數(shù)資料
| 型號(hào)： | FM24C128 |
| 廠商： | Fairchild Semiconductor Corporation |
| 元件分類： | DRAM |
| 英文描述： | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| 中文描述： | 該CAT24FC02是一個(gè)2 KB的EEPROM的國(guó)內(nèi)256個(gè)8位每字舉辦的串行CMOS |
| 文件頁數(shù)： | 10/13頁 |
| 文件大小： | 102K |
| 代理商： | FM24C128 |
10
www.fairchildsemi.com
FM24C128 Rev. B.1
F
Write Operations
BYTE WRITE
For byte write operation, two bytes of address are required after
the slave address. These two bytes select 1 out of the 16,384
locations in the memory. The master provides these two address
bytes and for each address byte received, FM24C128 responds
with an acknowledge pulse. Master then provides a byte of data
to be written into the memory. Upon receipt of this data, FM24C128
responds with an acknowledge pulse. The master then terminates
the transfer by generating a stop condition, at which time the
FM24C128 begins the internal write cycle to the memory. While
the internal write cycle is in progress the FM24C128 inputs are
disabled, and the device will not respond to any requests from the
master for the duration of t
WR
. Refer Figure 4 for the address,
acknowledge and data transfer sequence.
PAGE WRITE
To minimize write cycle time, FM24C128 offers Page Write
feature, which allows simultaneous programming of up to 64
contiguous bytes. To facilitate this feature, the memory array is
organized in terms of
“
Pages
”
. A Page consists of 64 contiguous
byte locations starting at every 64-Byte address boundary (for
example, starting at array address 0x0000, 0x0040, 0x0080 etc.).
Page Write operation is confined to a single page. In other words
a Page Write operation will not cross over to locations on the next
page but will
“
roll over
”
to the beginning of the same page
whenever end of page is reached and additional data bytes are a
continued to be provided. A Page Write operation can be initiated
to begin at any location within a page (starting address of the Page
Write operation need not be the starting address of a Page).
S
T
O
P
A
C
K
A
C
K
Bus Activity:
Master
SDA Line
1 0 1 0
Bus Activity
A
C
K
DATA n
DATA n+63
A
C
K
WORD
ADDRESS (1)
WORD
ADDRESS (0)
SLAVE
ADDRESS
S
T
A
R
T
S
T
O
P
A
C
K
Bus Activity:
Master
SDA Line
Bus Activity:
EEPROM
A
C
K
DATA
A
C
K
A
C
K
WORD
ADDRESS (1)
WORD
ADDRESS (0)
SLAVE
ADDRESS
S
T
A
R
T
Page Write is initiated in the same manner as the Byte Write
operation; but instead of terminating the cycle after transmitting
the first data byte, the master can further transmit up to 63 more
bytes. After the receipt of each byte, FM24C128 will respond with
an acknowledge pulse, increment the internal address counter to
the next address, and is ready to accept the next data. If the master
should transmit more than 64 bytes prior to generating the STOP
condition, the address counter will
“
roll over
”
and previously
loaded data will be re-loaded. As with the Byte Write operation, all
inputs are disabled until completion of the internal write cycle.
Refer Figure 5for the address, acknowledge, and data transfer
sequence.
Acknowledge Polling
Once the stop condition is issued to indicate the end of the host
’
s
write operation, the FM24C128 initiates the internal write cycle.
ACK polling can be initiated immediately. This involves issuing the
start condition followed by the slave address for a write operation.
If the FM24C128 is still busy with the write operation, no ACK will
be returned. If the FM24C128 has completed the write operation,
an ACK will be returned and the host can then proceed with the
next read or write operation.
Write Protection
Programming of the entire memory will not take place if the WP pin
of the FM24C128 is connected to V
CC
. The FM24C128 will
respond to slave and byte addresses; but if the memory accessed
is write protected by the WP pin, the FM24C128 will not generate
an acknowledge after the first byte of data has been received.
Thus the program cycle will not be started when the stop condition
is asserted.
Byte Write (Figure 4)
Page Write (Figure 5)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| FM24C16U | 16K-Bit Standard 2-Wire Bus Interface Serial EEPROM(16K位的標(biāo)準(zhǔn)兩線控制總線接口串行EEPROM) |
| FM24C256-SE | 256Kb FRAM Serial Memory |
| FM24C256LZYYX | 256 KBit 2-Wire Bus Interface Serial EEPROM with Write Protect |
| FM24C256FLZYYX | 256 KBit 2-Wire Bus Interface Serial EEPROM with Write Protect |
| FM24C256 | 256K-Bit 2-Wire Bus Interface Serial EEPROM with Write Protect(帶寫保護(hù)的256K位的兩線控制總線接口串行EEPROM) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FM24C128EMT8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:I2C Serial EEPROM |
| FM24C128EMT8X | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:I2C Serial EEPROM |
| FM24C128EMW8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:I2C Serial EEPROM |
| FM24C128EMW8X | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:I2C Serial EEPROM |
| FM24C128EN | 功能描述:電可擦除可編程只讀存儲(chǔ)器 RoHS:否 制造商:Atmel 存儲(chǔ)容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
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