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參數(shù)資料
| 型號(hào)： | MB84VA2103-10 |
| 廠商： | FUJITSU LTD |
| 元件分類： | 存儲(chǔ)器 |
| 英文描述： | 16M (x16) FLASH MEMORY & 2M (x 8) STATIC RAM |
| 中文描述： | SPECIALTY MEMORY CIRCUIT, PBGA48 |
| 封裝： | PLASTIC, FBGA-48 |
| 文件頁(yè)數(shù)： | 27/29頁(yè) |
| 文件大小： | 422K |
| 代理商： | MB84VA2103-10 |
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27
MB84VA2102
-10
/MB84VA2103
-10
CE2s Controlled Data Retention Mode (Note 3)
Notes:
1. In CE1s controlled data retention mode, input level of CE2s should be fixed Vccs to Vccs-0.2V or Vss
to 0.2V during data retention mode. Other input and input/output pins can be used between -0.3V to
Vccs+0.3V.
2. When CE1s is operating at the V
IH
min. level (2.2 V), the standby current is given by I
SB1
s during the
transition of V
CC
s from 3.6 to 2.2 V.
3. In CE2s controlled data retention mode, input and input/output pins can be used between
-0.3V to Vccs+0.3V.
I
PIN CAPACITANCE
Note:
Test conditions T
A
= 25°C, f = 1.0 MHz
I
HANDLING OF PACKAGE
Please handle this package carefully since the sides of packages are right angle.
I
CAUTION
1)The high voltage (VID) can not apply to address pins and control pins except RESET. Therefore, it can not
use autoselect and sector protect function by applying the high voltage (VID) to specific pins.
2)For the sector protection, since the high voltage (VID) can be applied to the RESET, it can be protected the
sector useing "Extended sector protect" command.
Parameter
Symbol
Parameter Description
Test Setup
Typ.
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0
T.B.D
T.B.D
pF
C
OUT
Output Capacitance
V
OUT
= 0
T.B.D
T.B.D
pF
C
IN2
Control Pin Capacitance
V
IN
= 0
T.B.D
T.B.D
pF
V
CC
s
2.7 V
GND
DATA RETENTION MODE
V
IH
V
IL
CE2s
t
CDR
t
R
0.2 V
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| MB84VA2104 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:16M (x 8) FLASH MEMORY & 1M (x 8) STATIC RAM |
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