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參數(shù)資料
| 型號(hào)： | MC34055 |
| 廠商： | Motorola, Inc. |
| 英文描述： | IEEE 802.3 10BASE-T TRANSCEIVER |
| 中文描述： | 的IEEE 802.3 10Base - T的收發(fā)器 |
| 文件頁數(shù)： | 11/16頁 |
| 文件大小： | 195K |
| 代理商： | MC34055 |
MC34055
11
MOTOROLA ANALOG IC DEVICE DATA
LOOP L Test Mode
If the Loop L pin is low, the MC34055 is in a test mode
whereby the data at the input pin (TX Data A/B) is being
looped back internally to the receive data pin(RX Data A/B).
In this mode the data path from the differential receiver
terminals to the receive data output pins (RX Data A/B) is
disconnected while the Smart Squelch functionality of the
differential receiver is still operational. This test mode allows
the DTE to test the MC34055 internal loop back circuitry
since the data is looped back to the receive circuitry as close
to the twisted pair interface as possible.
Signal Quality Error Test
The MC34055 also provides the ability to test the collision
detect circuitry without disabling either of the data paths. By
pulling the SQE EN L pin low, a collision test is provided to
the collision detect circuitry immediately following the last
edge of a transmitted 802.3 frame. The test verifies the
operability of the collision detect circuitry, operability is
announced by the assertion of the CTL H pin for a period
following a valid data transmission.
Jabber Detection
The transmit circuitry of the MC34055 has the ability to
monitor and shut down the differential driver in the event of a
jabber condition. If transmission activity ever exceeds 20 ms
minimum, the differential driver, the collision detect, and
internal loop back circuits are disabled. To announce the
presence of a jabber condition, both the CTL H and the JABB
H status output pins are asserted. In order to end the jabber
condition, the TX Data A/B input must stop toggling, or the TX
EN H pin must be pulled low for a minimum of 500 ms. The
status output pins have the ability to drive an external led and
were added to facilitize network manageability. The jabber
status outputs will not assert during power up or power down.
Full Duplex Mode
The MC34055 can be operated in a full–duplex mode if
required. When the FULLD L pin is pulled low the device will
enter the full duplex mode. This mode allows the transmitter
and driver to operate independently. Collision will not be
announced and the internal loop back operation is disabled.
The Signal Quality Error test, however, is still operational if
enabled.
Status Pins
The MC34055 has three status indicator pins capable of
sourcing or sinking enough current to support an external
LED. Status pin levels (“1” or “0”) report the condition of the
transceiver. Table 2 shows the combinations and
significance.
Table 2
Status Pin
Condition
di i
JABB H
CTL H
LNKFL H
“0”
“1”
X
Collision condition or Signal Quality Error test.
“1”
“1”
X
Jabber condition
X
X
“0”
Link Failure. Incorrect or nonexistent link pulses, or lack of data at the
receiver terminals.
X
X
“1”
Link “OK”. Receiving link pulses.
X
X
“0101
…
”
Link “OK”. Receiving valid data.
Test Select Pins
The MC34055 has three operation mode test select pins,
Loop L, SQE EN L and FULLD L. The level of the pin
determines the mode of operation. Table 3 shows the levels
and corresponding conditions of the status pins.
Table 3
Pin
Status
Condition
Loop L
“1”
Normal operating mode. Loop back occurs when the transmitter initiates and the receiver is receiving
link pulses. The RX EN H pin follows the TX EN H pin and the transmit data appears on the RX Data
A/B output pin being used.
“0”
Loop back test mode. The transmit circuit is looped back internally as close to the differential receive
circuit as possible. In this mode the RX EN H pin follows the TX EN H pin and the transmit data ap-
pears on the RX Data A/B output pin being used. Any received data other than link pulses are ignored
and the receiver will not unsquelch or announce collision.
SQE EN L
“0”
Normal operating mode. Concurrent transmit and receive activity results in a collision condition.
“1”
Test enabled. An internal test is run on the collision circuitry and the CTL H pin is asserted for a time
window following the last positive packet edge. Data transmission and reception is undisturbed.
FULLD L
“1”
Normal operating mode. Internal loop–back is operable and collision is announced.
“0”
Internal loop–back is disabled and collision will not be announced. Signal Quality Error test is
still operable.
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