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參數資料
| 型號： | MC34055DW |
| 廠商： | MOTOROLA INC |
| 元件分類： | 網絡接口 |
| 英文描述： | 5-V Battery-Backup Supervisors for RAM Retention 8-MSOP -40 to 85 |
| 中文描述： | DATACOM, ETHERNET TRANSCEIVER, PDSO24 |
| 封裝： | PLASTIC, SO-24 |
| 文件頁數： | 7/16頁 |
| 文件大小： | 280K |
| 代理商： | MC34055DW |
MC34055
7
MOTOROLA ANALOG IC DEVICE DATA
PIN FUNCTION DESCRIPTION
Pin
Symbol
Description
1
Clk Out
TTL/CMOS buffered 10 MHz clock output. This pin will source 400
μ
A and sink 16 mA.
2
TX Data A
CMOS transmit input pin. Data input at this pin is output to the TP media. The input will source
less than 175
μ
A and sink less than 20
μ
A.
3
TX Data B
Raised ECL transmit input pin. Data input at this pin is output to the TP media. The input can
source 40
μ
A for a high level input or 70
μ
A for a low level input.
4
TX EN H
TTL/CMOS transmit enable pin. Transmit is enabled when asserted high. The input will source
less than 175
μ
A and sink less than 20
μ
A.
5
Dig. Gnd
Digital ground
6
VCC(Dig/Ana)
Digital and analog VCC. With the current consumed at this pin and Pin 18, the device will
consume less than 180 mA at 5.0 Vdc.
7
Ana. Gnd
Analog ground
8
RX Data A
TTL/CMOS received data output pin. Data from the TP media is output at this pin. The output
will source 12 mA and sink 16 mA.
9
RX Data B
Raised ECL received data output pin. Data from the TP media is output at this pin.
10
RX EN H
TTL/CMOS received data output enable pin. This pin is asserted after the Smart Squelch
circuitry determines that there is valid data at the TP input pins and also when internal
loop–back is occurring. The output will source 12 mA and sink 16 mA. The receive data outputs
are forced high when this pin is low.
11
Loop L
TTL/CMOS Loopback test select. Asserting this pin causes the transmit data to be looped to
the receive circuit while the TP transmit driver sends a link pulse. The input will source less
than 175
μ
A and sink less than 20
μ
A.
12
LNKFL H
This pin is driven high to indicate a link fail state. When low, the pin will sink 20 mA to light an
LED. An usquelched condition due to valid data on the receive circuit will cause the pin to
transition high and low in 100 ms intervals.
13
JABB H
TTL/CMOS Jabber status pin. This pin is asserted when a Jabber condition is detected and will
source 12 mA and sink 16 mA.
14
CTL H
TTL/CMOS status pin. This pin pulled high when Jabber or Collision conditions are detected.
Also high for a time interval when a Signal Quality Error test is being performed. The pin will
source 12 mA and sink 16 mA.
15
RX–
The inverting terminal of the TP differential receiver.
16
RX+
The noninverting terminal of the TP differential receiver.
17
FULLD L
TTL/CMOS duplex mode select. When low, this pin forces the device to operate in full–duplex
mode. The input will source less than 175
μ
A and sink less than 20
μ
A.
18
Pwr VCC
Power supply pin. With the current consumed at this pin and Pin 6, the device will consume
less than 180 mA at 5.0 Vdc.
19
Pwr Gnd
Power ground pin.
20
TX–
The inverting terminal of the TP differential driver.
21
TX+
The noninverting terminal of the TP differential driver.
22
SQE EN L
TTL/CMOS Signal Quality Error test enable pin. Pulling this pin low allows test of the collision
detect circuitry without affecting the twisted pair channel. The input will source less than 175
μ
A
and sink less than 20
μ
A.
23
Clk–
TTL/CMOS clock oscillator pin. See Pin 24.
24
Clk+
TTL/CMOS clock oscillator pin. This pin is used with Pin 23 if the internal oscillator is to be free
run with a crystal. The oscillator can also be directly driven with a TTL/CMOS clock signal at
this pin. The oscillator frequency should be 10 MHz with a duty cycle of 50
±
20%.
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