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參數資料
| 型號： | MC68332GVFC20 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-Bit Modular Microcontroller |
| 中文描述： | 32-BIT, 20.97 MHz, MICROCONTROLLER, PQFP132 |
| 封裝： | PLASTIC, QFP-132 |
| 文件頁數： | 32/88頁 |
| 文件大小： | 446K |
| 代理商： | MC68332GVFC20 |
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MOTOROLA
32
MC68332
MC68332TS/D
CSPAR1 contains five 2-bit fields that determine the functions of corresponding chip-select pins.
CSPAR1[15:10] are not used. These bits always read zero; writes have no effect.
At reset, either the alternate function (01) or chip-select function (11) can be encoded. DATA pins are
driven to logic level one by a weak interval pull-up during reset. Encoding is for chip-select function un-
less a data line is held low during reset. Note that bus loading can overcome the weak pull-up and hold
pins low during reset. The following table shows the hierarchical selection method that determines the
reset functions of pins controlled by CSPAR1.
A pin programmed as a discrete output drives an external signal to the value specified in the port C
pin data register (PORTC), with the following exceptions:
1.
2.
No discrete output function is available on pins BR, BG, or BGACK.
ADDR23 provides E-clock output rather than a discrete output signal.
When a pin is programmed for discrete output or alternate function, internal chip-select logic still func-
tions and can be used to generate DSACK or AVEC internally on an address match.
Port size is determined when a pin is assigned as a chip select. When a pin is assigned to an 8-bit port,
the chip select is asserted at all addresses within the block range. If a pin is assigned to a 16-bit port,
the upper/lower byte field of the option register selects the byte with which the chip select is associated.
CSPAR1
—Chip Select Pin Assignment Register 1
$YFFA46
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
CSPA1[4]
CSPA1[3]
CSPA1[2]
CSPA1[1]
CSPA1[0]
RESET:
0
0
0
0
0
0
DATA7
1
DATA
[7:6]
1
DATA
[7:5]
1
DATA
[7:4]
1
DATA
[7:3]
1
Table 14 CSPAR1 Pin Assignments
CSPAR0 Field
CSPA1[4]
CSPA1[3]
CSPA1[2]
CSPA1[1]
CSPA1[0]
Chip Select Signal
CS10
CS9
CS8
CS7
CS6
Alternate Signal
ADDR23
ADDR22
ADDR21
ADDR20
ADDR19
Discrete Output
ECLK
PC6
PC5
PC4
PC3
Table 15 Reset Pin Function of CS[10:6]
Data Bus Pins at Reset
Chip-Select/Address Bus Pin Function
DATA7
DATA6
DATA5
DATA4
DATA3
CS10/
ADDR23
CS9/
ADDR22
CS8/
ADDR21
CS7/
ADDR20
CS6/
ADDR19
1
1
1
1
1
CS10
CS9
CS8
CS7
CS6
1
1
1
1
0
CS10
CS9
CS8
CS7
ADDR19
1
1
1
0
X
CS10
CS9
CS8
ADDR20 ADDR19
1
1
0
X
X
CS10
CS9
ADDR21 ADDR20 ADDR19
1
0
X
X
X
CS10
ADDR22 ADDR21 ADDR20 ADDR19
0
X
X
X
X
ADDR23 ADDR22 ADDR21 ADDR20 ADDR19
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