- 您現在的位置：買賣IC網 > PDF目錄371043 > MC68332TS (Motorola, Inc.) 32-Bit Modular Microcontroller PDF資料下載
參數資料
| 型號： | MC68332TS |
| 廠商： | Motorola, Inc. |
| 英文描述： | 32-Bit Modular Microcontroller |
| 中文描述： | 32位微控制器模塊 |
| 文件頁數： | 42/88頁 |
| 文件大小： | 446K |
| 代理商： | MC68332TS |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁當前第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁
MOTOROLA
42
MC68332
MC68332TS/D
mask lower-priority interrupts during exception processing, and it is decoded by modules that have re-
quested interrupt service to determine whether the current interrupt acknowledge cycle pertains to
them.
Modules that have requested interrupt service decode the IP value placed on the address bus at the
beginning of the interrupt acknowledge cycle, and if their requests are at the specified IP level, respond
to the cycle. Arbitration between simultaneous requests of the same priority is performed by means of
serial contention between module interrupt arbitration (IARB) field bit values.
Each module that can make an interrupt service request, including the SIM, has an IARB field in its con-
figuration register. An IARB field can be assigned a value from %0001 (lowest priority) to %1111 (high-
est priority). A value of %0000 in an IARB field causes the CPU to process a spurious interrupt
exception when an interrupt from that module is recognized.
Because the EBI manages external interrupt requests, the SIM IARB value is used for arbitration be-
tween internal and external interrupt requests. The reset value of IARB for the SIM is %1111, and the
reset IARB value for all other modules is %0000. Initialization software must assign different IARB val-
ues in order to implement an arbitration scheme.
Each module must have a unique IARB value. When two or more IARB fields have the same nonzero
value, the CPU interprets multiple vector numbers simultaneously, with unpredictable consequences.
Arbitration must always take place, even when a single source requests service. This point is important
for two reasons: the CPU interrupt acknowledge cycle is not driven on the external bus unless the SIM
wins contention, and failure to contend causes an interrupt acknowledge bus cycle to be terminated by
a bus error, which causes a spurious interrupt exception to be taken.
When arbitration is complete, the dominant module must place an interrupt vector number on the data
bus and terminate the bus cycle. In the case of an external interrupt request, because the interrupt ac-
knowledge cycle is transferred to the external bus, an external device must decode the mask value and
respond with a vector number, then generate bus cycle termination signals. If the device does not re-
spond in time, a spurious interrupt exception is taken.
The periodic interrupt timer (PIT) in the SIM can generate internal interrupt requests of specific priority
at predetermined intervals. By hardware convention, PIT interrupts are serviced before external inter-
rupt service requests of the same priority. Refer to 3.2.7 Periodic Interrupt Timer
for more information.
3.8.2 Interrupt Processing Summary
A summary of the interrupt processing sequence follows. When the sequence begins, a valid interrupt
service request has been detected and is pending.
A. The CPU finishes higher priority exception processing or reaches an instruction boundary.
B. Processor state is stacked. The contents of the status register and program counter are saved.
C. The interrupt acknowledge cycle begins:
1.
FC[2:0] are driven to %111 (CPU space) encoding.
2.
The address bus is driven as follows. ADDR[23:20] = %1111; ADDR[19:16] = %1111,
which indicates that the cycle is an interrupt acknowledge CPU space cycle; ADDR[15:4]
= %111111111111; ADDR[3:1] = the level of the interrupt request being acknowledged;
and ADDR0 = %1.
3.
Request priority level is latched into the IP field in the status register from the address bus.
D. Modules or external peripherals that have requested interrupt service decode the request level
in ADDR[3:1]. If the request level of at least one interrupting module or device is the same as
the value in ADDR[3:1], interrupt arbitration contention takes place. When there is no conten-
tion, the spurious interrupt monitor asserts BERR, and a spurious interrupt exception is pro-
cessed.
E. After arbitration, the interrupt acknowledge cycle can be completed in one of three ways:
相關PDF資料 |
PDF描述 |
|---|---|
| MC68332GCFC16 | 32-Bit Modular Microcontroller |
| MC68332GCFC20 | 32-Bit Modular Microcontroller |
| MC68332GCFV20 | 32-Bit Modular Microcontroller |
| MC68332GCFVV16 | 32-Bit Modular Microcontroller |
| MC68332GMFC16 | 32-Bit Modular Microcontroller |
相關代理商/技術參數 |
參數描述 |
|---|---|
| MC68332VFC16 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:32-Bit Modular Microcontroller |
| MC68332VFC20 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:32-Bit Modular Microcontroller |
| MC68332VFV16 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:32-Bit Modular Microcontroller |
| MC68332VFV20 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:32-Bit Modular Microcontroller |
| MC68334 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Technical Supplement |
發布緊急采購，3分鐘左右您將得到回復。