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參數資料
| 型號： | TMJ320C6211GLW167 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | CONNECTOR ACCESSORY |
| 中文描述： | 連接器附件 |
| 文件頁數： | 21/83頁 |
| 文件大小： | 1176K |
| 代理商： | TMJ320C6211GLW167 |
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TMS320C6211, TMS320C6211B
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS073K
AUGUST 1998
REVISED MARCH 2004
21
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
§
PLLV and PLLG are not part of external voltage supply or ground. See the CLOCK/PLL documentation for information on how to connect these
pins.
A = Analog signal (PLL Filter)
#
The EMU0 and EMU1 pins are internally pulled up with 30-k
resistors; therefore, for emulation and normal operation, no external
pullup/pulldown resistors are necessary. However, for boundary scan operation, pull down the EMU1 and EMU0 pins with a dedicated 1-k
resistor.
Terminal Functions (Continued)
SIGNAL
NAME
TYPE
IPD/
IPU
DESCRIPTION
NO.
HOST-PORT INTERFACE (HPI) (CONTINUED)
HD15
HD14
HD13
HD12
HD11
HD10
HD9
HD8
HD7
HD6
HD5
HD4
HD3
HD2
HD1
HD0
HAS
HCS
HDS1
HDS2
HRDY
B14
C14
A15
C15
A16
B16
C16
B17
A18
C17
B18
C19
C20
D18
D20
E20
E18
F20
E19
F18
H19
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPD
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPD
Host-port data
Used for transfer of data, address, and control
Also controls initialization of DSP modes at reset via pullup/pulldown resistors
Device Endian mode
HD8: 0
– Big Endian
1
Little Endian
Boot mode
HD[4:3]: 00 – HPI boot
01
8-bit ROM boot with default timings
16 bit ROM boot with default timings
10
16-bit ROM boot with default timings
11
32-bit ROM boot with default timings
d f t
f f d t dd
t l
I/O/Z
I
I
I
I
Host address strobe
Host chip select
Host data strobe 1
Host data strobe 2
Host ready (from DSP to host)
EMIF
CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY
IPU
IPU
IPU
IPU
IPU
IPU
IPU
Byte-write enables for most types of memory
b di
tl
IPU
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k
IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-k
resistor should be used.)
O
CE3
CE2
CE1
CE0
BE3
BE2
BE1
BE0
V6
W6
W18
V17
V5
Y4
U19
V20
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
Memory space enables
Enabled by bits 28 through 31 of the word address
Only one asserted during any external data access
Byte-enable control
Decoded from the two lowest bits of the internal address
Can be directly connected to SDRAM read and write mask signal (SDQM)
t d t SDRAM
it
k i
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