- 您現在的位置：買賣IC網 > PDF目錄382646 > TMX320C6202BGLW167 (Texas Instruments, Inc.) FIXED-POINT DIGITAL SIGNAL PROCESSORS PDF資料下載
參數資料
| 型號： | TMX320C6202BGLW167 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數字信號處理 |
| 英文描述： | FIXED-POINT DIGITAL SIGNAL PROCESSORS |
| 中文描述： | 定點數字信號處理器 |
| 文件頁數： | 63/83頁 |
| 文件大小： | 1176K |
| 代理商： | TMX320C6202BGLW167 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁當前第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁
TMS320C6211, TMS320C6211B
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS073K
AUGUST 1998
REVISED MARCH 2004
63
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
HOST-PORT INTERFACE TIMING
timing requirements for host-port interface cycles [C6211]
(see Figure 33, Figure 34, Figure 35,
and Figure 36)
NO.
C6211
150
C6211
167
UNIT
MIN
5
4
4P
4P
5
3
5
3
MAX
1
2
3
4
10
11
12
13
t
su(SELV-HSTBL)
t
h(HSTBL-SELV)
t
w(HSTBL)
t
w(HSTBH)
t
su(SELV-HASL)
t
h(HASL-SELV)
t
su(HDV-HSTBH)
t
h(HSTBH-HDV)
Setup time, select signals
§
valid before HSTROBE low
Hold time, select signals
§
valid after HSTROBE low
Pulse duration, HSTROBE low
Pulse duration, HSTROBE high between consecutive accesses
Setup time, select signals
§
valid before HAS low
Hold time, select signals
§
valid after HAS low
Setup time, host data valid before HSTROBE high
Hold time, host data valid after HSTROBE high
Hold time, HSTROBE low after HRDY low. HSTROBE should not be inactivated
until HRDY is active (low); otherwise, HPI writes will not complete properly.
ns
ns
ns
ns
ns
ns
ns
ns
14
t
h(HRDYL-HSTBL)
2
ns
18
19
t
su(HASL-HSTBL)
t
h(HSTBL-HASL)
Setup time, HAS low before HSTROBE low
Hold time, HAS low after HSTROBE low
2
2
ns
ns
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.
§
Select signals include: HCNTL[1:0], HR/W, and HHWIL.
switching characteristics over recommended operating conditions during host-port interface
cycles [C6211]
(see Figure 33, Figure 34, Figure 35, and Figure 36)
NO.
PARAMETER
C6211
150
C6211
167
UNIT
MIN
MAX
15
15
5
6
t
d(HCS-HRDY)
t
d(HSTBL-HRDYH)
t
d(HSTBL-HDLZ)
t
d(HDV-HRDYL)
t
oh(HSTBH-HDV)
t
d(HSTBH-HDHZ)
t
d(HSTBL-HDV)
t
d(HSTBH-HRDYH)
t
d(HASL-HRDYH)
Delay time, HCS to HRDY
Delay time, HSTROBE low to HRDY high
#
1
3
ns
ns
7
Delay time, HSTROBE low to HD low impedance for an HPI read
2
ns
8
9
15
Delay time, HD valid to HRDY low
Output hold time, HD valid after HSTROBE high
Delay time, HSTROBE high to HD high impedance
2P
4
2P
15
15
ns
ns
ns
3
3
16
Delay time, HSTROBE low to HD valid
3
15
ns
17
20
Delay time, HSTROBE high to HRDY high
||
Delay time, HAS low to HRDY high
3
3
15
15
ns
ns
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.
HCS enables HRDY, and HRDY is always low when HCS is high. The case where HRDY goes high when HCS falls indicates that HPI is busy
completing a previous HPID write or READ with autoincrement.
#
This parameter is used during an HPID read. At the beginning of the first half-word transfer on the falling edge of HSTROBE, the HPI sends the
request to the EDMA internal address generation hardware, and HRDY remains high until the EDMA internal address generation hardware loads
the requested data into HPID.
||
This parameter is used after the second half-word of an HPID write or autoincrement read. HRDY remains low if the access is not an HPID write
or autoincrement read. Reading or writing to HPIC or HPIA does not affect the HRDY signal.
相關PDF資料 |
PDF描述 |
|---|---|
| TMX320C6203BGLW167 | FIXED-POINT DIGITAL SIGNAL PROCESSORS |
| TMX320C6211BGLW167 | FIXED-POINT DIGITAL SIGNAL PROCESSORS |
| TMPP320C6202BGLW167 | FIXED-POINT DIGITAL SIGNAL PROCESSORS |
| TMX320C6202BGLZ167 | FIXED-POINT DIGITAL SIGNAL PROCESSORS |
| TMX320C6203BGLZ167 | FIXED-POINT DIGITAL SIGNAL PROCESSORS |
相關代理商/技術參數 |
參數描述 |
|---|---|
| TMX320C6202BGLZ167 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PROCESSORS |
| TMX320C6202BGNY167 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PROCESSORS |
| TMX320C6202BGNZ167 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PROCESSORS |
| TMX320C6202BPYP167 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PROCESSORS |
| TMX320C6202GDP167 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PROCESSORS |
發布緊急采購，3分鐘左右您將得到回復。