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參數資料

型號：	TMX320C6203BGLW167
廠商：	Texas Instruments, Inc.
元件分類：	數字信號處理
英文描述：	FIXED-POINT DIGITAL SIGNAL PROCESSORS
中文描述：	定點數字信號處理器
文件頁數：	20/83頁
文件大小：	1176K
代理商：	TMX320C6203BGLW167

TMS320C6211, TMS320C6211B

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS073K

AUGUST 1998

REVISED MARCH 2004

POST OFFICE BOX 1443

HOUSTON, TEXAS 77251

1443

Terminal Functions

SIGNAL

NAME

TYPE

IPD/

IPU

DESCRIPTION

NO.

CLOCK/PLL

CLKIN

IPD

Clock Input

Clock output at device speed

The CLK1EN bit in the EMIF GBLCTL register controls the CLKOUT1 pin.

CLK1EN = 0:

CLKOUT1 is disabled

CLK1EN = 1:

CLKOUT1 enabled to clock [default]

Clock output at half of device speed

When the CLKOUT2 pin is enabled, the CLK2EN bit in the EMIF global control register

(GBLCTL) controls the CLKOUT2 pin.

CLK2EN = 0:

CLKOUT2 is disabled

CLK2EN = 1:

CLKOUT1 enabled to clock [default]

CLKOUT1

IPD

CLKOUT2

Y12

IPD

CLKMODE0

IPU

Clock mode select

Selects whether the CPU clock frequency = input clock frequency x4 or x1

PLLV

PLLG

PLLF

PLL analog V

connection for the low-pass filter

PLL analog GND connection for the low-pass filter

PLL low-pass filter connection to external components and a bypass capacitor

JTAG EMULATION

JTAG test-port mode select

JTAG test-port data out

JTAG test-port data in

JTAG test-port clock

JTAG test-port reset

Emulation pin 5. Reserved for future use, leave unconnected.

Emulation pin 4. Reserved for future use, leave unconnected.

Emulation pin 3. Reserved for future use, leave unconnected.

Emulation pin 2. Reserved for future use, leave unconnected.

Emulation pin 1

Emulation pin 0

RESETS AND INTERRUPTS

Device reset

Nonmaskable interrupt

Edge-driven (rising edge)

Any noise on the NMI pin may trigger an NMI interrupt; therefore, if the NMI pin is not used, it is

recommended that the NMI pin be grounded versus relying on the IPD.

TMS

TDO

TDI

TCK

TRST

EMU5

EMU4

EMU3

EMU2

EMU1

EMU0

B12

C11

B10

D10

IPU

IPD

IPU

O/Z

I/O/Z

RESET

A13

IPU

NMI

C13

IPD

EXT_INT7

EXT_INT6

EXT_INT5

EXT_INT4

External interrupts

Edge-driven

Polarity independently selected via the External Interrupt Polarity Register bits

(EXTPOL [3 0])

(EXTPOL.[3:0])

IPU

HOST-PORT INTERFACE (HPI)

Host interrupt (from DSP to host)

Host control

selects between control, address, or data registers

Host control

selects between control, address, or data registers

Host half-word select

first or second half-word (not necessarily high or low order)

Host read or write select

HINT

HCNTL1

HCNTL0

HHWIL

HR/W

I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground

IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k

IPD or IPU resistor. To pull up a signal to the opposite

supply rail, a 1-k

resistor should be used.)

J20

G19

G18

H20

G20

IPU

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