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參數資料
| 型號： | AD7575JN |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | LC2MOS 5 us 8-Bit ADC with Track/Hold |
| 中文描述： | 1-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDIP18 |
| 封裝： | 0.300 INCH, PLASTIC, DIP-18 |
| 文件頁數： | 2/12頁 |
| 文件大小： | 146K |
| 代理商： | AD7575JN |
REV. B
–2–
AD7575–SPECIFICATIONS
(V
DD
= +5 V, V
REF
= +1.23 V, AGND = DGND = 0 V; f
CLK
= 4 MHz external;
all specifications T
MIN
to T
MAX
unless otherwise noted)
Parameter
J, A Versions
1
K, B Versions
S Version
T Version
Units
Conditions/Comments
ACCURACY
Resolution
Total Unadjusted Error
Relative Accuracy
Minimum Resolution for Which
No Missing Codes Is Guaranteed
Full-Scale Error
+25
°
C
T
MIN
to T
MAX
Offset Error
2
+25
°
C
T
MIN
to T
MAX
8
±
2
±
1
8
±
1
±
1/2
8
±
2
±
1
8
±
1
±
1/2
Bits
LSB max
LSB max
8
8
8
8
Bits max
±
1
±
1
±
1
±
1
±
1
±
1
±
1
±
1
LSB max
LSB max
Full-Scale TC Is Typically 5 ppm/
°
C
±
1/2
±
1/2
±
1/2
±
1/2
±
1/2
±
1/2
±
1/2
±
1/2
LSB max
LSB max
Offset TC Is Typically 5 ppm/
°
C
ANALOG INPUT
Voltage Range
DC Input Impedance
Slew Rate, Tracking
SNR
3
0 to 2 V
REF
10
0.386
45
0 to 2 V
REF
10
0.386
45
0 to 2 V
REF
0 to 2 V
REF
10
0.386
45
Volts
M
min
V/
μ
s max
dB min
1 LSB = 2 V
REF
/256; See Figure 16
10
0.386
45
V
IN
= 2.46 V p-p @ 10 kHz; See Figure 11
REFERENCE INPUT
V
REF
(For Specified Performance)
I
REF
1.23
500
1.23
500
1.23
500
1.23
500
Volts
μ
A max
±
5%
LOGIC INPUTS
CS
,
RD
V
INL
, Input Low Voltage
V
INH
, Input High Voltage
I
IN
, Input Current
+25
°
C
T
to T
C
IN
, Input Capacitance
3
0.8
2.4
0.8
2.4
0.8
2.4
0.8
2.4
V max
V min
±
1
±
10
10
±
1
±
10
10
±
1
±
10
10
±
1
±
10
10
μ
A max
μ
A max
pF max
V
IN
= 0 or V
DD
V
IN
= 0 or V
DD
CLK
V
lNL
, Input Low Voltage
V
INH
, Input High Voltage
I
INL
, Input Low Current
I
INH
, Input High Current
0.8
2.4
700
700
0.8
2.4
700
700
0.8
2.4
800
800
0.8
2.4
800
800
V max
V min
μ
A max
μ
A max
V
INL
= 0 V
V
INH
= V
DD
LOGIC OUTPUTS
BUSY
, DB0 to DB7
V
OL
, Output Low Voltage
V
, Output High Voltage
DB0 to DB7
Floating State Leakage Current
Floating State Output Capacitance
3
0.4
4.0
0.4
4.0
0.4
4.0
0.4
4.0
V max
V min
I
SINK
= 1.6 mA
I
SOURCE
= 40
μ
A
±
1
10
±
1
10
±
10
10
±
10
10
μ
A max
pF max
V
OUT
= 0 to V
DD
CONVERSION TIME
4
With External Clock
With Internal Clock, T
A
= +25
°
C
5
5
15
5
5
15
5
5
15
5
5
15
μ
s
μ
s min
μ
s max
f
CLK
= 4 MHz
Using Recommended Clock
Components Shown in Figure 15
POWER REQUIREMENTS
5
V
DD
I
DD
Power Dissipation
Power Supply Rejection
+5
6
15
±
1/4
+5
6
15
±
1/4
+5
7
15
±
1/4
+5
7
15
±
1/4
Volts
mA max
mW typ
LSB max
±
5% for Specified Performance
Typically 3 mA with V
DD
= +5 V
4.75 V
≤
V
DD
≤
5.25 V
NOTES
1
Temperature ranges are as follows:
J, K Versions; 0
°
C to +70
°
C
A, B Versions; –25
°
C to +85
°
C
S, T Versions; –55
°
C to +125
°
C
2
Offset error is measured with respect to an ideal first code transition that occurs at 1/2 LSB.
3
Sample tested at +25
°
C to ensure compliance.
4
Accuracy may degrade at conversion times other than those specified.
5
Power supply current is measured when AD7575 is inactive i.e., when
CS
=
RD
=
BUSY
= logic HIGH.
Specifications subject to change without notice.
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