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參數資料
| 型號： | MC34115DW |
| 廠商： | MOTOROLA INC |
| 元件分類： | 編解碼器 |
| 英文描述： | CONTINUOUSLY VARIABLE SLOPE DELTA MODULATOR/DEMODULATOR |
| 中文描述： | CVSD, CVSD CODEC, PDSO16 |
| 封裝： | PLASTIC, SO-16 |
| 文件頁數： | 3/16頁 |
| 文件大小： | 359K |
| 代理商： | MC34115DW |
MC34115
3
MOTOROLA ANALOG IC DEVICE DATA
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 12 V, VEE = Gnd, TA = 0
°
to 70
°
C, unless otherwise noted.)
Characteristic
Unit
Max
Typ
Min
Symbol
Propagation Delay Times (Note 1)
Clock Trigger to Digital Output
CL = 25 pF to Gnd
Clock Trigger to Coincidence Output
CL = 25 pF to Gnd, RL = 4.0 k
to VCC
Coincidence Output Voltage – Low Logic Stage (IOL(Con) = 3.0 mA)
Coincidence Output Leakage Current – High Logic State (VOH = 15 V)
Applied Digital Threshold Voltage Range (Pin 12)
μ
s
tPLH
tPHL
tPLH
tPHL
–
–
–
–
1.0
0.8
1.0
0.8
3.0
3.0
3.5
2.5
VOL(Con)
IOH(Con)
Vth
II(th)
–
0.12
0.25
Vdc
–
0.01
0.5
μ
A
1.2
–
VCC – 2.0
Vdc
Digital Threshold Input Current
1.2 V
≤
Vth
≤
VCC – 2.0 V
VIL Applied to Pins 13, 14 and 15
VIH Applied to Pins 13, 14 and 15
Maximum Integrator Amplifier Output Current
μ
A
–
–
–
5.0
–50
–10
IO
Iref
zref
ε
r
±
5.0
–
–
mA
VCC/2 Generator Maximum Output Current (Source Only)
VCC/2 Generator Output Impedance (0 to –10 mA)
VCC/2 Generator Tolerance (4.75 V
≤
VCC
≤
16.5 V)
Logic Input Voltage (Pins 13, 14 and 15)
Low Logic State
High Logic State
–10
–
–
mA
–
3.0
6.0
–
–
±
3.5
%
Vdc
VIL
VIH
VEE
–
–
Vth – 0.4
16.5
Vth + 0.4
Dynamic Total Loop Offset Voltage (Note 3) (Figures 3, 4 and 5)
IGC = 33
μ
A, VCC = 12 V
TA = 25
°
C
0
°
C
≤
TA
≤
+70
°
C
IGC = 33
μ
A, VCC = 5.0 V
TA = 25
°
C
0
°
C
≤
TA
≤
+70
°
C
Digital Output Voltage (Pin 9)
IOL = 3.6 mA
IOH = –0.35 mA
Syllabic Filter Applied Voltage (Pin 3) (Figure 2)
Σ
Voffset
mV
–
–
±
2.5
±
3.0
±
7.0
±
10
–
–
±
4.0
±
4.5
±
8.0
±
12
Vdc
VOL
VOH
VI(Syl)
IInt
–
0.1
0.4
–
VCC – 1.0
3.2
VCC – 0.2
–
VCC
Vdc
Integrating Current (Figure 2)
IGC = 12
μ
A
IGC = 1.5 mA
IGC = 3.0 mA
Dynamic Integrating Current Match (Figure 6) (IGC = 1.5 mA)
Input Current – High Logic State (VIH = 16.5 V)
Digital Data Input
Clock Input
Encode/Decode Input
8.0
1.4
2.75
10
1.5
3.0
12
1.6
3.25
μ
A
mA
mA
VO(Ave)
IIH
–
±
100
±
300
mV
μ
A
–
–
–
–
–
–
5.0
5.0
5.0
Input Current – Low Logic State (VIL = 0 V)
Digital Data Input
Clock Input
Encode/Decode Input
Clock Input, VIL = 0.4 V
IIL
μ
A
–10
–360
–36
–72
–
–
–
–
–
–
–
–
NOTES:
1.All propagation delay times measured 50% to 50% from the negative going (from VCC to +0.4 V) edge of the clock.
2.Devices should not be operated at these values. The “Electrical Characteristics” provide conditions for actual device operation.
3.Dynamic total loop offset (
Σ
Voffset) equals VIO (comparator) (Figure 3) minus VIOX (Figure 5). The input offset voltages of the analog
comparator and of the integrator amplifier include the effects of input offset current through the input resistors. The slope polarity switch
current mismatch appears as an average voltage across the 10 k integrator resistor. The clock frequency is 16 kHz. Idle channel
performance is guaranteed if this dynamic total loop offset is less than one–half of the change in integrator output voltage during one
clock cycle (ramp step size).
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