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參數資料
| 型號： | MC34115DW |
| 廠商： | MOTOROLA INC |
| 元件分類： | 編解碼器 |
| 英文描述： | CONTINUOUSLY VARIABLE SLOPE DELTA MODULATOR/DEMODULATOR |
| 中文描述： | CVSD, CVSD CODEC, PDSO16 |
| 封裝： | PLASTIC, SO-16 |
| 文件頁數： | 5/16頁 |
| 文件大小： | 359K |
| 代理商： | MC34115DW |
MC34115
5
MOTOROLA ANALOG IC DEVICE DATA
Pin 13 – Digital Data Input
In a decode application, the digital data stream is applied
to Pin 13. In an encoder it may be unused or may be used to
transmit a signaling message under the control of Pin 15. It is
an inverting input with respect to Pin 9. When Pins 9 and 13
are connected, a toggle flip–flop is formed and a forced idle
channel pattern can be transmitted. The digital data input
level should be maintained for 0.5
μ
s before and after the
clock trigger for proper clocking.
Pin 14 – Clock Input
The clock input determines the data rate of the codec
circuit. A 16 k bit rate requires a 16 kHz clock. The switching
threshold of the clock input is set by Pin 12. The shift register
circuit toggles on the falling edge of the clock input. The
minimum high time for the clock input is 300 ns and minimum
low time is 900 ns.
Pin 15 – Encode/Decode
This pin controls the connection of the analog input
comparator and the digital input comparator to the internal
shift register. If high, the result of the analog comparison will
be clocked into the register on the falling edge at Pin 14. If low,
the digital input state will be entered. This allows use of the IC
as an encoder/decoder or simplex codec without external
parts. Furthermore, it allows non–voice patterns to be forced
onto the transmission line through Pin 13 in an encoder.
Pin 16 – VCC
The power supply range is from 4.75 to 16.5 V between
Pin VCC and VEE.
Figure 1. Power Supply Current
VCC
60 mV
+
10 k
0.05
0.1
Clock
ICC
CVSD
MC34115
1.0 k
1.0 k
5.0 k
–
VCC
10 k
0.05
0.1
Clock
(Note 2)
0.1
IGC
CVSD
MC34115
VB
Rx
Digital
Output
(Note 1)
Digital Data
Input
IInt
A
+
–
NOTES:
1.Digital Output = Digital Data Input
2.For static testing, the clock is only necessary for
preconditioning to obtain proper state for a given input.
Figure 2. IGCR – Gain Control Range and IInt –
Integrating Current
IGC
VB
Rx
5.0 k
11
9
7
6
8
5
4
1
2
3
13
12
10
16
15
14
11
7
6
8
5
4
1
2
3
13
12
10
16
15
14
9
Rx
10
μ
F
10
μ
F
0.1
0.1
10 k
0.1
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