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參數資料
| 型號： | MC68332AVFC20 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-Bit Modular Microcontroller |
| 中文描述： | 32-BIT, 20.97 MHz, MICROCONTROLLER, PQFP132 |
| 封裝： | PLASTIC, QFP-132 |
| 文件頁數： | 57/88頁 |
| 文件大小： | 446K |
| 代理商： | MC68332AVFC20 |
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MC68332
MC68332TS/D
MOTOROLA
57
5.2.9 Frequency Measurement (FQM)
FQM counts the number of input pulses to a TPU channel during a user-defined window period. The
function has single shot and continuous modes. No pulses are lost between sample windows in contin-
uous mode. The user selects whether to detect pulses on the rising or falling edge. This function is in-
tended for high speed measurement; measurement of slow pulses with noise rejection can be made
with PTA.
5.2.10 Hall Effect Decode (HALLD)
This function decodes the sensor signals from a brushless motor, along with a direction input from the
CPU, into a state number. The function supports two- or three-sensor decoding. The decoded state
number is written into a COMM channel, which outputs the required commutation drive signals. In ad-
dition to brushless motor applications, the function can have more general applications, such as decod-
ing “option” switches.
5.3 Programmer's Model
The TPU control register address map occupies 512 bytes. The “Access” column in the TPU address
map below indicates which registers are accessible only at the supervisor privilege level and which can
be assigned to either the supervisor or user privilege level, according to the value of the SUPV bit in the
TPUMCR.
Y = M111, where M represents the logic state of the module mapping (MM) bit in the SIMCR.
Table 22 TPU Address Map
Access
S
S
S
S
S
S
S
S
S
S
S/U
S/U
S/U
S/U
S
S
S
S
S
S
Address
$YFFE00
$YFFE02
$YFFE04
$YFFE06
$YFFE08
$YFFE0A
$YFFE0C
$YFFE0E
$YFFE10
$YFFE12
$YFFE14
$YFFE16
$YFFE18
$YFFE1A
$YFFE1C
$YFFE1E
$YFFE20
$YFFE22
$YFFE24
$YFFE26
15
8
7
0
TPU MODULE CONFIGURATION REGISTER (TPUMCR)
TEST CONFIGURATION REGISTER (TCR)
DEVELOPMENT SUPPORT CONTROL REGISTER (DSCR)
DEVELOPMENT SUPPORT STATUS REGISTER (DSSR)
TPU INTERRUPT CONFIGURATION REGISTER (TICR)
CHANNEL INTERRUPT ENABLE REGISTER (CIER)
CHANNEL FUNCTION SELECTION REGISTER 0 (CFSR0)
CHANNEL FUNCTION SELECTION REGISTER 1 (CFSR1)
CHANNEL FUNCTION SELECTION REGISTER 2 (CFSR2)
CHANNEL FUNCTION SELECTION REGISTER 3 (CFSR3)
HOST SEQUENCE REGISTER 0 (HSQR0)
HOST SEQUENCE REGISTER 1 (HSQR1)
HOST SERVICE REQUEST REGISTER 0 (HSRR0)
HOST SERVICE REQUEST REGISTER 1 (HSRR1)
CHANNEL PRIORITY REGISTER 0 (CPR0)
CHANNEL PRIORITY REGISTER 1 (CPR1)
CHANNEL INTERRUPT STATUS REGISTER (CISR)
LINK REGISTER (LR)
SERVICE GRANT LATCH REGISTER (SGLR)
DECODED CHANNEL NUMBER REGISTER (DCNR)
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