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參數資料
| 型號： | MC68332AVFC20 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-Bit Modular Microcontroller |
| 中文描述： | 32-BIT, 20.97 MHz, MICROCONTROLLER, PQFP132 |
| 封裝： | PLASTIC, QFP-132 |
| 文件頁數： | 84/88頁 |
| 文件大小： | 446K |
| 代理商： | MC68332AVFC20 |
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MOTOROLA
84
MC68332
MC68332TS/D
7 Standby RAM with TPU Emulation RAM
The TPURAM module contains a 2-Kbyte array of fast (two bus cycle) static RAM, which is especially
useful for system stacks and variable storage. Alternately, it can be used by the TPU as emulation RAM
for new timer algorithms.
7.1 Overview
The TPURAM can be mapped to any 4-Kbyte boundary in the address map, but must not overlap the
module control registers. (Overlap makes the registers inaccessible.) Data can be read or written in
bytes, word, or long words. TPURAM responds to both program and data space accesses. Data can be
read or written in bytes, words, or long words. The TPURAM is powered by V
DD
in normal operation.
During power-down, the TPURAM contents are maintained by power on standby voltage pin V
STBY
.
Power switching between sources is automatic.
Access to the TPURAM array is controlled by the RASP field in TRAMMCR. This field can be encoded
so that TPURAM responds to both program and data space accesses. This allows code to be executed
from TPURAM, and permits the use of program counter relative addressing mode for operand fetches
from the array.
An address map of the TPURAM control registers follows. All TPURAM control registers are located in
supervisor data space.
Y = M111, where M is the logic state of the MM bit in the SIMCR.
7.2 TPURAM Register Block
There are three TPURAM control registers: the RAM module configuration register (TRAMMCR), the
RAM test register (TRAMTST), and the RAM array base address registers (TRAMBAR).
There is an 8-byte minimum register block size for the module. Unimplemented register addresses are
read as zeros, and writes have no effect.
7.3 TPURAM Registers
TSTOP —Stop Control
0 = RAM array operates normally.
1 = RAM array enters low-power stop mode.
This bit controls whether the RAM array is in stop mode or normal operation. Reset state is zero, for
normal operation. In stop mode, the array retains its contents, but cannot be read or written by the CPU.
Table 28 TPURAM Control Register Address Map
Access
S
S
S
Address
$YFFB00
$YFFB02
$YFFB04
$YFFB06–
$YFFB3F
15
8 7
0
TPURAM MODULE CONFIGURATION REGISTER (TRAMMCR)
TPURAM TEST REGISTER (TRAMTST)
TPURAM BASE ADDRESS REGISTER (TRAMBAR)
NOT USED
TRAMMCR
—TPURAM Module Configuration Register
$YFFB00
15
14
13
12
11
10
9
8
7
0
STOP
0
0
0
0
0
0
RASP
NOT USED
RESET:
0
0
0
0
0
0
0
1
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