- 您現在的位置：買賣IC網 > PDF目錄371076 > MC908QL2V (Motorola, Inc.) Microcontrollers PDF資料下載
參數資料
| 型號： | MC908QL2V |
| 廠商： | Motorola, Inc. |
| 英文描述： | Microcontrollers |
| 中文描述： | 微控制器 |
| 文件頁數： | 163/222頁 |
| 文件大小： | 2861K |
| 代理商： | MC908QL2V |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁當前第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁第215頁第216頁第217頁第218頁第219頁第220頁第221頁第222頁
Initialization/Application Information
MC68HC908QL4 MC68HC908QL3 MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
163
14.9.14 High-Speed LIN Operation
High-speed LIN operation does not necessarily require any reconfiguration of the SLIC module,
depending upon what maximum LIN bit rate is desired. Several factors affect the performance of the SLIC
module at LIN speeds higher than 20 kbps, all of which are functions of the speed of the SLIC clock and
the prescaler of the digital filter. The tightest constraint comes from the need to maintain ±1.5% accuracy
with the master node timing. This requires that the SLIC module be able to sample the incoming data
stream accurately enough to guarantee that accuracy.
Table 14-5
shows the maximum LIN bit rates
allowable to maintain this accuracy.
The above numbers assume a perfect input waveforms into the SLCRX pin, where 1 and 0 bits are of
equal length and are exactly the correct length for the appropriate speed. Factors such as physical layer
wave shaping and ground shift can affect the symmetry of these waveforms, causing bits to appear
shortened or lengthened as seen by the SLIC module. The user must take these factors into account and
base the maximum speed upon the shortest possible bit time that the SLIC module may observe, factoring
in all physical layer effects. On some LIN physical layer devices it is possible to turn off wave shaping
circuitry for high-speed operation, removing this portion of the physical layer error.
The digital receive filter can also affect high speed operation if it is set too low and begins to filter out valid
message traffic. Under ideal conditions, this will not happen, as the digital filter maximum speeds
allowable are higher than the speeds allowed for ±1.5% accuracy. If the digital receive filter prescaler is
set to divide- by-4; however, the filter delay is very close to the ±1.5% accuracy maximum bit time.
For example, with a SLIC clock of 4 MHz, the SLIC module is capable of maintaining ±1.5% accuracy up
to 60,000 bps. If the digital receive filter prescaler is set to divide-by-4, this means that the filter will only
pass message traffic which is 62,500 bps or slower under ideal circumstances. This is only a difference
of 2,500 bps (4.17% of the nominal valid message traffic speed). In this case, the user must ensure that
with all errors accounted for, no bit will appear shorter than 16
μ
s
(1 bit at 62,500 bps) or the filter will block that bit. This is far too narrow a margin for safe design practices.
The better solution would be to reduce the filter prescaler, increasing the gap between the filter cut-off
point and the nominal speed of valid message traffic. Changing the prescaler to divide by 2 in this example
gives a filter cut-off of 125,000 bps, which is 60,000 bps faster than the nominal speed of the LIN bus and
much less likely to interfere with valid message traffic.
To ensure that all valid messages pass the filter stage in high-speed operation, it is best to ensure that
the filter cut-off point is at least 2 times the nominal speed of the fastest message traffic to appear on the
bus. Refer to
Table 14-6
for a more complete list of the digital receive filter delays as they relate to the
maximum LIN bus frequency.
Table 14-7
repeats much of the data found in
Table 14-6
; however, the filter
Table 14-5. Maximum LIN Bit Rates for High-Speed Operation
SLIC Clock (MHz)
Maximum LIN Bit Rate
for ±1% SLIC Accuracy
(Bits / Second)
Maximum LIN Bit Rate
for ±1.5% SLIC Accuracy
(Bits / Second)
8
80,000
120,000
6.4
64,000
96,000
4.8
48,000
72,000
4
40,000
60,000
3.2
32,000
48,000
2.4
24,000
36,000
2
20,000
30,000
相關PDF資料 |
PDF描述 |
|---|---|
| MC908QL4DT | Microcontrollers |
| MC908QL4DW | Microcontrollers |
| MC908QL4M | Microcontrollers |
| MC908QL4V | Microcontrollers |
| MC912DG128x | microcontroller unit 16BIT DEVICE |
相關代理商/技術參數 |
參數描述 |
|---|---|
| MC908QL3C | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Microcontrollers |
| MC908QL3CDWE | 功能描述:8位微控制器 -MCU NITRON LIN RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數據總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| MC908QL3DT | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Microcontrollers |
| MC908QL3DW | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Microcontrollers |
| MC908QL3M | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Microcontrollers |
發布緊急采購，3分鐘左右您將得到回復。