- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄371076 > MC908QL2V (Motorola, Inc.) Microcontrollers PDF資料下載
參數(shù)資料
| 型號： | MC908QL2V |
| 廠商： | Motorola, Inc. |
| 英文描述： | Microcontrollers |
| 中文描述： | 微控制器 |
| 文件頁數(shù)： | 168/222頁 |
| 文件大小： | 2861K |
| 代理商： | MC908QL2V |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁當前第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁第215頁第216頁第217頁第218頁第219頁第220頁第221頁第222頁
Slave LIN Interface Controller (SLIC) Module
MC68HC908QL4 MC68HC908QL3 MC68HC908QL2 Data Sheet, Rev. 4
168
Freescale Semiconductor
The error also comes into effect with transmitted bit times. Using the previous example with a SLCBT
value of 34, transmitted bits will appear as 34 SLIC clock periods long. This is one SLIC clock short of the
proper length. Depending on the frequency of the SLIC clock, one period of the SLIC clock might be a
large or a small fraction of one ideal bit time. Raising the frequency of the SLIC clock will reduce this error
relative to the ideal bit time, improving the resolution of the SLIC clock relative to the bit rate of the bus.
In any case, the error is still one SLIC clock cycle. Raising the SLIC clock frequency, however, requires
programming a higher value for SLCBT to maintain the same target bit rate.
Smaller values of SLCBT combined with higher values of the SLIC clock frequency (smaller clock period)
will give faster bit rates, but the SLIC clock period becomes an increasingly significant portion of one bit
time.
Because BTM mode does not perform any synchronization and relies on the accuracy of the data
provided by the user software to set its sample point and generate transmitted bits, the constraint on
maximum speeds is only limited to the limits imposed by the digital filter delay and the SLIC input clock.
Because the digital filter delay cannot be less than 16 SLIC clock cycles, the fastest possible pulse which
would pass the filter is 16 clock periods at 8 MHz, or 500,000 bits/second. The values shown in
Table 14-7
are the same values shown in
Table 14-8
and indicate the absolute fastest bit rates which could just pass
the minimum digital filter settings (prescaler = divide by 1) under perfect conditions.
Because perfect conditions are almost impossible to attain, more robust values must be chosen for bit
rates. For reliable communication, it is best to ensure that a bit time is no smaller 2x–3x longer than the
filter delay on the digital receive filter. This is true in LIN or BTM mode and ensures that valid data bits
which have been shortened due to ground shift, asymmetrical rise and fall times, etc., are accepted by
the filter without exception. This would translate to 2x to 3x reduction in the maximum speeds shown in
Table 14-7
. Recommended maximum bit rates are shown in
Table 14-8
, and ensure that a single bit time
is at least twice the length of one filter delay value. If system noise is not adequately filtered out it might
be necessary to change the prescaler of the filter and lower the bit rate of the communication. If valid
communications are being absorbed by the filter, corrective action must be taken to ensure that either the
bit rate is reduced or whatever physical fault is causing bit times to shorten is corrected (ground offset,
asymmetrical rise/fall times, insufficient physical layer supply voltage, etc.).
Table 14-8. Recommended Maximum Bit Rates
for BTM Operation Due to Digital Filter
SLIC
Clock
(MHz)
Maximum BTM
Bit Rate with
Digital RX Filter
Set to
÷
4
(Bits / Second)
Maximum BTM
Bit Rate with
Digital RX Filter
Set to
÷
3
(Bits / Second)
Maximum BTM
Bit Rate with
Digital RX Filter
Set to
÷
2
(Bits / Second)
120,000
(1)
Maximum BTM
Bit Rate with
Digital RX Filter
Set to
÷
1
(Bits / Second)
120,000
(1)
120,000
(1)
120,000
(1)
120,000
(1)
8
62,500
83,333
1. Bit rates over 120,000 bits per second are not recommended for BTM communications, as
physical layer delay between the TX and RX pins can cause the stop bit of a byte to be
missampled as the last data bit. This could result in a byte framing error.
6.4
50,000
66,667
100,000
4.8
37,500
50,000
75,000
4
31,250
41,667
62,500
3.2
25,000
33,333
50,000
100,000
2.4
18,750
25,000
37,500
75,000
2
15,625
20,833
31,250
62,500
相關PDF資料 |
PDF描述 |
|---|---|
| MC908QL4DT | Microcontrollers |
| MC908QL4DW | Microcontrollers |
| MC908QL4M | Microcontrollers |
| MC908QL4V | Microcontrollers |
| MC912DG128x | microcontroller unit 16BIT DEVICE |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MC908QL3C | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Microcontrollers |
| MC908QL3CDWE | 功能描述:8位微控制器 -MCU NITRON LIN RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| MC908QL3DT | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Microcontrollers |
| MC908QL3DW | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Microcontrollers |
| MC908QL3M | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Microcontrollers |
發(fā)布緊急采購，3分鐘左右您將得到回復。