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| 型號： | 61LV256 |
| 廠商： | Integrated Silicon Solution, Inc. |
| 英文描述： | CONNECTOR ACCESSORY |
| 中文描述： | 連接器附件 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大小： | 100K |
| 代理商： | 61LV256 |
ISSI
IS61LV256
2-6
Integrated Silicon Solution, Inc.
Rev. F 0296
SR81995LV61
AC WAVEFORMS
WRITE CYCLE NO. 1 (
WE
Controlled)
(1,2)
DATA-IN VALID
DATA UNDEFINED
t
WC
t
SCE
t
AW
t
HA
t
PWE
t
HZWE
HIGH-Z
t
LZWE
t
SA
t
SD
t
HD
ADDRESS
CE
WE
D
OUT
D
IN
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,3)
(Over Operating Range)
-12 ns
Min.
-15 ns
Min.
-20 ns
Min.
-25 ns
Min.
Symbol
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
(4)
t
SD
t
HD
t
HZWE
(2)
t
LZWE
(2)
Parameter
Max.
Max.
Max.
Max.
Unit
Write Cycle Time
12
—
15
—
20
—
25
—
ns
CE
to Write End
8
—
10
—
13
—
15
—
ns
Address Setup Time to Write End
8
—
10
—
15
—
20
—
ns
Address Hold from Write End
0
—
0
—
0
—
0
—
ns
Address Setup Time
0
—
0
—
0
—
0
—
ns
WE
Pulse Width
8
—
10
—
13
—
15
—
ns
Data Setup to Write End
6
—
8
—
10
—
12
—
ns
Data Hold from Write End
0
—
0
—
0
—
0
—
ns
WE
LOW to High-Z Output
—
6
—
7
—
8
—
10
ns
WE
HIGH to Low-Z Output
0
—
0
—
0
—
0
—
ns
Notes:
1. Test conditions assume signal transition times of 3ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured
±
500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of
CE
LOW and
WE
LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
4. Tested with
OE
HIGH.
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