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參數資料
| 型號： | 61SP6464 |
| 廠商： | Integrated Silicon Solution, Inc. |
| 英文描述： | 64K x 64 SYNCHRONOUS PIPELINE STATIC RAM |
| 中文描述： | 64K的× 64 SYNCHRONOU擰管道靜態RAM |
| 文件頁數： | 15/19頁 |
| 文件大小： | 130K |
| 代理商： | 61SP6464 |
IS61SP6464
ISSI
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
01/14/04
15
SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS
(Over Operating Range)
-117 MHz
Min.
-100 MHz
Min.
Symbol
Parameter
Max.
Max.
Unit
t
KC
Cycle Time
9.2
—
10
—
ns
t
KH
Clock High Time
3.4
—
4
—
ns
t
KL
Clock Low Time
3.4
—
4
—
ns
t
KQ
Clock Access Time
—
5
—
5
ns
t
KQX
(3)
Clock High to Output Invalid
1.5
—
2.5
—
ns
t
KQLZ
(3,4)
Clock High to Output Low-Z
0
—
0
—
ns
t
KQHZ
(3,4)
Clock High to Output High-Z
2
5
2
5
ns
t
OEQ
Output Enable to Output Valid
—
5
—
5
ns
t
OEQX
(3)
Output Disable to Output Invalid
0
—
0
—
ns
t
OELZ
(3,4)
Output Enable to Output Low-Z
0
—
0
—
ns
t
OEHZ
(3,4)
Output Disable to Output High-Z
2
5
2
5
ns
t
AS
Address Setup Time
2.5
—
2.5
—
ns
t
SS
Address Status Setup Time
2.5
—
2.5
—
ns
t
CES
Chip Enable Setup Time
2.5
—
2.5
—
ns
t
AH
Address Hold Time
0.5
—
0.5
—
ns
t
SH
Address Status Hold Time
0.5
—
0.5
—
ns
t
CEH
Chip Enable Hold Time
0.5
—
0.5
—
ns
t
ZZS
ZZ Standby
(1)
2
—
2
—
cyc
t
ZZREC
ZZ Recovery
(2)
2
—
2
—
cyc
Notes:
1. The assertion of ZZ allows the SRAM to enter a lower power state than when deselected within the time specified. Data
retention is guaranteed when ZZ is asserted and clock remains active.
2.
ADSC
and
ADSP
must not be asserted for at least 2 cyc after leaving ZZ state.
3. Guaranteed but not 100% tested. This parameter is periodically sampled.
4. Tested with load in Figure 2.
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