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參數資料
| 型號： | 62LV1024SC |
| 廠商： | BRILLIANCE SEMICONDUCTOR, INC. |
| 元件分類： | SRAM |
| 英文描述： | Very Low Power/Voltage CMOS SRAM 128K X 8 bit |
| 中文描述： | 非常低功率/電壓CMOS SRAM的128K的× 8位 |
| 文件頁數： | 7/11頁 |
| 文件大?。?/td> | 383K |
| 代理商： | 62LV1024SC |
Revision 2.2
April 2001
7
R0201-BS62LV1024
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and WE low.
All signals must be active to initiate a write and any one signal can terminate a write by going
inactive. The data input setup and hold timing should be referenced to the second transition edge
of the signal that terminates the write.
3. T
WR
is measured from the earlier of CE1 or WE going high or CE2 going low at the end of write
cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the
outputs must not be applied.
5. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low
transitions or after the WE transition, output remain in a high impedance state.
6. OE is continuously low (OE = V
IL
).
7. D
OUT
is the same phase of write data of this write cycle.
8. D
OUT
is the read data of next address.
9. If CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the data input
signals of opposite phase to the outputs must not be applied to them.
10. Transition is measured 500mV from steady state with C
L
= 5pF as shown in Figure 1B. The
parameter is guaranteed but not 100% tested.
11. T
CW
is measured from the later of CE1 going low or CE2 going high to the end of write.
WRITE CYCLE2
(1,6)
BSI
BS62LV1024
t
WC
t
CW
(11)
(11)
t
CW
(2)
t
WP
t
AW
t
WHZ
(4,10)
t
AS
t
WR2
(3)
t
DH
t
DW
D
IN
D
OUT
WE
CE2
CE1
ADDRESS
(5)
(5)
t
DH
(7)
(8)
(8,9)
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