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參數資料
| 型號： | 68HC05J5A |
| 廠商： | Motorola, Inc. |
| 英文描述： | 8-Bit Microcontroller Units (MCU).(8位微控制器) |
| 中文描述： | 8位微控制器單元（MCU）。（8位微控制器） |
| 文件頁數： | 32/106頁 |
| 文件大小： | 1069K |
| 代理商： | 68HC05J5A |
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GENERAL RELEASE SPECIFICATION
July 16, 1999
MOTOROLA
4-6
INTERRUPTS
MC68HC05J5A
REV 2.1
IRQF - IRQ Interrupt Request Flag
Writing to the IRQF flag bit will have no effect on it. If the additional setting of IRQF
flag bit is not cleared in the IRQ service routine and the IRQE enable bit remains
set the CPU will re-enter the IRQ interrupt sequence continuously until either the
IRQF flag bit or the IRQE enable bit is clear. The IRQF latch is cleared by reset.
1 =
Indicates that an IRQ request is pending.
0 =
Indicates that no IRQ request triggered by pins PA0-3 or IRQ is
pending. The IRQF flag bit is cleared once the IRQ vector is fetched
AND if IRQE1 is also cleared. If IRQE1 is set, then the only way of
clearing IRQF flag is by writing a logic one to IRQR bit. The IRQF
flag bit can be cleared, regardless of the status of the IRQE1 bit, by
writing a logic one to the IRQR acknowledge bit to clear the IRQ
latch and also conditioning the external IRQ sources to be inactive
(if the level sensitive interrupts are enabled via mask option). Doing
so before exiting the service routine will mask out additional
occurrences of the IRQF.
IRQE1 - PA7 Interrupt Enable
The IRQE1 bit enables/disables the IRQF1 flag bit to initiate an IRQ interrupt
sequence.
1 =
Enables IRQF1 interrupt, that is, the IRQF1 flag bit can generate an
interrupt sequence. Execution of the STOP or WAIT instructions will
leave the IRQE1 bit to be UNAFFECTED.
0 =
The IRQF1 flag bit cannot generate an interrupt sequence. Reset
clears the IRQE1 enable bit, thereby disabling PA7 interrupts.
IRQE - IRQ Interrupt Enable
The IRQE bit enables/disables the IRQF flag bit to initiate an IRQ interrupt
sequence.
1 =
Enables IRQF interrupt, that is, the IRQF flag bit can generate an
interrupt sequence. Reset sets the IRQE enable bit, thereby
enabling IRQ interrupts once the I-bit is cleared. Execution of the
STOP or WAIT instructions causes the IRQE bit to be set in order to
allow the external IRQ to exit these modes.
0 =
The IRQF flag bit cannot generate an interrupt sequence.
4.5.2 OPTIONAL EXTERNAL INTERRUPTS (PA0-PA3)
The IRQ interrupt can also be triggered by the inputs on the PA0 thru PA3 port
pins if enabled by a single mask option. If enabled, the lower four bits of Port A
can activate the IRQ interrupt function, and the interrupt operation will be the
same as for inputs to the IRQ pin. This mask option of PA0-3 interrupt allow all of
these input pins to be OR’ed with the input present on the IRQ pin. All PA0 thru
PA3 pins must be selected as a group as an additional IRQ interrupt. All the PA0-3
interrupt sources are also controlled by the IRQE enable bit.
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