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參數資料
| 型號： | 68HC05J5A |
| 廠商： | Motorola, Inc. |
| 英文描述： | 8-Bit Microcontroller Units (MCU).(8位微控制器) |
| 中文描述： | 8位微控制器單元（MCU）。（8位微控制器） |
| 文件頁數： | 61/106頁 |
| 文件大小： | 1069K |
| 代理商： | 68HC05J5A |
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July 16, 1999
GENERAL RELEASE SPECIFICATION
MC68HC05J5A
REV 2.1
16-BIT TIMER
MOTOROLA
9-3
The timer counter registers (TCNTH, TCNTL) shown in
Figure 9-3
are read-only
locations which contain the current high and low bytes of the 16-bit free-running
counter. Writing to the timer registers has no effect. Reset of the device presets
the timer counter to $FFFC.
The TCNTL latch is a transparent read of the LSB until the a read of the TCNTH
takes place. A read of the TCNTH latches the LSB into the TCNTL location until
the TCNTL is again read. The latched value remains fixed even if multiple reads of
the TCNTH take place before the next read of the TCNTL. Therefore, when read-
ing the MSB of the timer at TCNTH the LSB of the timer at TCNTL must also be
read to complete the read sequence.
During power-on-reset (POR), the counter is initialized to $FFFC and begins
counting after the oscillator start-up delay. Because the counter is 16 bits and pre-
ceded by a fixed divide-by-four prescaler, the value in the counter repeats every
262, 144 internal bus clock cycles (524, 288 oscillator cycles).
When the free-running counter rolls over from $FFFF to $0000, the timer overflow
flag bit (T1OF) is set in the T1SR. When the T1OF is set, it can generate an inter-
rupt if the timer overflow interrupt enable bit (T1OIE) is also set in the T1CR. The
T1OF flag bit can only be reset by reading the TCNTL after reading the T1SR.
Other than clearing any possible T1OF flags, reading the TCNTH and TCNTL in
any order or any number of times does not have any effect on the 16-bit free-run-
ning counter.
NOTE
To prevent interrupts from occurring between readings of the TCNTH and TCNTL,
set the I bit in the condition code register (CCR) before reading TCNTH and clear
the I bit after reading TCNTL.
9.2
ALTERNATE COUNTER REGISTERS (ACNTH, ACNTL)
The functional block diagram of the 16-bit free-running timer counter and alternate
counter registers is shown in
Figure 9-4
. The alternate counter registers behave
the same as the timer counter registers, except that any reads of the alternate
BIT 7
Bit15
BIT 6
Bit14
BIT 5
Bit13
BIT 4
Bit12
BIT 3
Bit11
BIT 2
Bit10
BIT 1
Bit9
BIT 0
Bit8
TCNTH
$0018
R
W
reset:
1
1
1
1
1
1
1
1
TCNTL
$0019
R
W
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
reset:
1
1
1
1
1
1
0
0
Figure 9-3. 16-Bit Timer Counter Registers (TCNTH, TCNTL)
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