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| 型號： | 68HC05PL4 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 8-Bit Microcontroller Units (MCU).(8位微控制器) |
| 中文描述： | 8位微控制器單元（MCU）。（8位微控制器） |
| 文件頁數(shù)： | 54/98頁 |
| 文件大小： | 1019K |
| 代理商： | 68HC05PL4 |
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GENERAL RELEASE SPECIFICATION
April 30, 1998
MOTOROLA
9-4
16-BIT PROGRAMMABLE TIMER
MC68HC05PL4
REV 2.0
9.2
ALTERNATE COUNTER REGISTERS (ACRH, ACRL)
The functional block diagram of the 16-bit free-running timer counter and alternate
counter registers is shown in
Figure 9-4
. The alternate counter registers behave
the same as the timer registers, except that any reads of the alternate counter will
not have any effect on the TOF flag bit and Timer interrupts. The alternate counter
registers include a transparent buffer latch on the LSB of the 16-bit timer counter.
Figure 9-4. Alternate Counter Block Diagram
The alternate counter registers (ACRH, ACRL) shown in
Figure 9-5
are read-only
locations which contain the current high and low bytes of the 16-bit free-running
counter. Writing to the alternate counter registers has no effect. Reset of the
device presets the timer counter to $FFFC.
The ACRL latch is a transparent read of the LSB until the a read of the ACRH
takes place. A read of the ACRH latches the LSB into the ACRL location until the
ACRL is again read. The latched value remains fixed even if multiple reads of the
ACRH take place before the next read of the ACRL. Therefore, when reading the
MSB of the timer at ACRH the LSB of the timer at ACRL must also be read to
complete the read sequence.
During power-on-reset (POR), the counter is initialized to $FFFC and begins
counting after the oscillator start-up delay. Because the counter is sixteen bits and
preceded by a fixed divide-by-four prescaler, the value in the counter repeats
every 262,144 internal bus clock cycles (524,288 oscillator cycles).
Reading the ACRH and ACRL in any order or any number of times does not have
any effect on the 16-bit free-running counter or the TOF flag bit.
BIT 7
BIT 6
ACRH6
BIT 5
ACRH5
BIT 4
ACRH4
BIT 3
ACRH3
BIT 2
ACRH2
BIT 1
ACRH1
BIT 0
ACRH0
ACRH
$001A
R ACRH7
W
reset:
1
1
1
1
1
1
1
1
ACRL
$001B
R
W
ACRL7
ACRL6
ACRL5
ACRL4
ACRL3
ACRL2
ACRL1
ACRL0
reset:
1
1
1
1
1
1
0
0
Figure 9-5. Alternate Counter Registers (ACRH, ACRL)
ACRH ($001A)
TMR LSB
16-BIT COUNTER
÷
4
INTERNAL
CLOCK
(XTAL
÷
2)
RESET
ACRL ($001B)
INTERNAL
DATA
BUS
($FFFC)
READ
ACRH
READ
ACRL
READ
LATCH
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