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參數(shù)資料
| 型號(hào)： | 68HC05PL4 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 8-Bit Microcontroller Units (MCU).(8位微控制器) |
| 中文描述： | 8位微控制器單元（MCU）。（8位微控制器） |
| 文件頁數(shù)： | 59/98頁 |
| 文件大小： | 1019K |
| 代理商： | 68HC05PL4 |
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April 30, 1998
GENERAL RELEASE SPECIFICATION
MC68HC05PL4
REV 2.0
16-BIT PROGRAMMABLE TIMER
MOTOROLA
9-9
OCIE - OUTPUT COMPARE INTERRUPT ENABLE
This read/write bit enables interrupts caused by an active signal on the TCMP
pin. Reset clears the OCIE bit.
1 =
Output compare interrupts enabled.
0 =
Output compare interrupts disabled.
TOIE - TIMER OVERFLOW INTERRUPT ENABLE
This read/write bit enables interrupts caused by a timer overflow. Reset clears
the TOIE bit.
1 =
Timer overflow interrupts enabled.
0 =
Timer overflow interrupts disabled.
IEDG - INPUT CAPTURE EDGE SELECT
The state of this read/write bit determines whether a positive or negative transi-
tion on the TCAP pin triggers a transfer of the contents of the timer register to
the input capture register. Resets have no effect on the IEDG bit.
1 =
Positive edge (low to high transition) triggers input capture.
0 =
Negative edge (high to low transition) triggers input capture.
OLVL - OUTPUT COMPARE OUTPUT LEVEL SELECT
The state of this read/write bit determines whether a logic one or a logic zero
appears on the TCMP when a successful output compare occurs. Resets clear
the OLVL bit.
1 =
TCMP goes high on output compare.
0 =
TCMP goes low on output compare.
9.5.1 Miscellaneous Control and Status Register for Timer16
The Miscellaneous Control and Status Register shown in
Figure 9-11
performs
the following functions:
Configure the I/O port pin PA2 as input pin for TCAP signal
Configure the I/O port pin PA3 as output pin for TCMP signal
TCAPEN - TIMER INPUT CAPTURE ENABLE
The bit configures port pin PA2 for Timer16 input capture function (TCAP). At
power-on-reset, this bit is cleared, PA2 is a standard I/O port pin, TCAP to the
Timer16 is pulled high.
1 =
PA2 pin configured as TCAP for timer input capture
0 =
PA2 pin as standard I/O port pin
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
0
BIT 2
BIT 1
BIT 0
MICSR
$001C
R
W
IRQEN
IRQS
TCMPEN TCAPEN
LED
COPON
POR
reset:
0
0
0
0
0
0
0
1
Figure 9-11. Miscellaneous Control and Status Register (MISCR)
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