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參數(shù)資料
| 型號： | FM20L08 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 1Mbit Bytewide FRAM Memory ? Extended Temp |
| 中文描述： | 為1Mbit FRAM存儲器Bytewide？擴(kuò)展級溫度 |
| 文件頁數(shù)： | 5/14頁 |
| 文件大小： | 153K |
| 代理商： | FM20L08 |
FM20L08 - Extended Temp.
Rev. 1.4
Oct. 2005
Page 5 of 14
Supply Voltage Monitor
An internal voltage monitor circuit continuously
checks the V
DD
supply voltage. When V
DD
is below
the specified threshold V
TP
, the monitor asserts the
/LVL signal to an active-low state. The FM20L08
locks out access to the memory when V
DD
is below
the trip voltage. This prevents the system from
accessing memory when V
DD
is too low and
inadvertently corrupting the data. The /LVL signal
should not be used as a system reset signal because
the system host may attempt to write data to the
FM20L08 below its specified operating voltage. The
/LVL pin may be used as a status indicator that the
memory is locked out.
On power up, the /LVL signal will begin in a low
state signifying that V
DD
is below the V
TP
threshold. It
will remain low as long as V
DD
is below that level.
Once V
DD
rises above V
TP
, a hold-off timer will begin
creating the delay t
PULV
. Once this delay has elapsed,
the /LVL signal will go high or inactive. At this time
the memory can be accessed. The memory is ready
for access prior to t
PU
as shown in the Electrical
Specifications section. The /LVL signal will remain
high until V
DD
drops below the threshold.
Software Write Protection
The 128Kx8 address space is divided into 8 sectors
(blocks) of 16Kx8 each. Each sector can be
individually software write-protected and the settings
are nonvolatile. A unique address and command
sequence invokes the write protection mode.
To modify write protection, the system host must
issue six read commands and two write commands.
The specific sequence of read addresses must be
provided in order to access to the write protect mode.
Following the read address sequence, the host must
write a data byte that specifies the desired protection
state of each sector. For confirmation, the system
must then write the complement of the protection byte
immediately following the protection byte. Any error
that occurs including read addresses in the wrong
order, issuing a seventh read address, or failing to
complement the protection value will leave the write
protection unchanged.
The write-protect state machine monitors all
addresses, taking no action until the write-protect
read/write sequence occurs. During the address
sequence, each read will occur as a valid operation
and data from the corresponding addresses will be
driven onto the data bus. Any address that occurs out
of sequence will cause the software protection state
machine to start over. After the address sequence is
completed, the next operation must be a write cycle.
The data byte contains the write-protect settings. This
value will not be written to the memory array, so the
write address is ignored. Rather the byte will be held
pending the next cycle, which must be a write of the
data complement to the protection settings. If the
complement is correct, the write protect settings will
be updated. If not, the process is aborted and the
address sequence starts over. The data value written
after the correct six addresses will not be entered into
memory.
The protection data byte consists of 8-bits, each
associated with the write protect state of a sector.
Setting a bit to 1 write protects the corresponding
sector; a 0 enables writes for that sector. The
following table shows the write-protect sectors with
the corresponding bit that controls the write-protect
setting.
Write Protect Sectors – 16K x8 blocks
Sector 7
1FFFFh – 1C000h
Sector 6
1BFFFh – 18000h
Sector 5
17FFFh – 14000h
Sector 4
13FFFh – 10000h
Sector 3
0FFFFh – 0C000h
Sector 2
0BFFFh – 08000h
Sector 1
07FFFh – 04000h
Sector 0
03FFFh – 00000h
The write-protect address sequence follows:
1.
05555h *
2.
1AAAAh
3.
03333h
4.
1CCCCh
5.
100FFh
6.
0FF00h
7.
1AAAAh
8.
1CCCCh
9.
0FF00h
10.
00000h
* If /CE is low entering the sequence, then an
address of 00000h must precede 05555h.
The address sequence provides a very secure way of
modifying the protection. The correct address
sequence has a 1 in 5 x 10
30
chance of occurring
accidentally. A flow chart of the entire write protect
operation is shown in Figure 2. As mentioned above,
write-protect settings are nonvolatile. The factory
default is unprotected.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FM20L08_07 | 制造商:RAMTRON 制造商全稱:RAMTRON 功能描述:1Mbit Bytewide FRAM Memory - Industrial Temp. |
| FM20L08-55-T | 制造商:Ramtron International Corporation 功能描述:128Kx8, 3V |
| FM20L08-60-TG | 功能描述:F-RAM 1M (128Kx8) 60ns 3.3 RoHS:否 存儲容量:512 Kbit 組織:64 K x 8 接口:SPI 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 封裝:Tube 制造商:Cypress Semiconductor |
| FM20L08-60-TG1 | 功能描述:F-RAM 1M (128Kx8) 60ns 3.3 RoHS:否 存儲容量:512 Kbit 組織:64 K x 8 接口:SPI 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 封裝:Tube 制造商:Cypress Semiconductor |
| FM20L08-60-TG1TR | 功能描述:F-RAM 1M (128Kx8) 60ns 3.3 RoHS:否 存儲容量:512 Kbit 組織:64 K x 8 接口:SPI 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 封裝:Tube 制造商:Cypress Semiconductor |
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