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參數資料
| 型號： | 62C1024L |
| 廠商： | Integrated Silicon Solution, Inc. |
| 英文描述： | 128K x 8 LOW POWER CMOS STATIC RAM |
| 中文描述： | 128K的× 8低功耗CMOS靜態RAM |
| 文件頁數： | 1/11頁 |
| 文件大小： | 65K |
| 代理商： | 62C1024L |
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. E
11/26/03
1
IS62C1024L
ISSI
Copyright 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
DESCRIPTION
The
ISSI
IS62C1024L is a low power,131,072-word by 8-bit
CMOS static RAM. It is fabricated using
ISSI
's high-performance
CMOS technology. This highly reliable process coupled
with innovative circuit design techniques, yields higher
performance and low power consumption devices.
When
CE1
is HIGH or CE2 is LOW (deselected), the
device assumes a standby mode at which the power
dissipation can be reduced by using CMOS input levels.
Easy memory expansion is provided by using two Chip
Enable inputs,
CE1
and CE2. The active LOW Write
Enable (
WE
) controls both writing and reading of the
memory.
The IS62C1024L is available in 32-pin plastic SOP and
TSOP (type 1) packages.
FUNCTIONAL BLOCK DIAGRAM
128K x 8 LOW POWER CMOS STATIC RAM
FEATURES
High-speed access time: 35, 70 ns
Low active power: 450 mW (typical)
Low standby power: 150 μW (typical) CMOS
standby
Output Enable (
OE
) and two Chip Enable
(
CE1
and CE2) inputs for ease in applications
Fully static operation: no clock or refresh
required
TTL compatible inputs and outputs
Single 5V (±10%) power supply
A0-A16
CE1
CE2
OE
WE
128K x 8
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
VDD
I/O
DATA
CIRCUIT
I/O0-I/O7
DECEMBER 2003
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