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參數(shù)資料
| 型號(hào)： | 68HC05BD2 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 8-Bit Microcontroller Units (MCU).(8位微控制器) |
| 中文描述： | 8位微控制器單元（MCU）。（8位微控制器） |
| 文件頁(yè)數(shù)： | 33/85頁(yè) |
| 文件大小： | 302K |
| 代理商： | 68HC05BD2 |
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SECTION 4: INTERRUPTS
MOTOROLA
Page 23
MC68HC05BD7 Rev. 2.0
GENERAL RELEASE SPECIFICATION
routine, but the IRQ pin has not returned back to high, no further interrupt will be generated.
The interrupt logic recognizes negative edge transitions and pulses (special case of
negative edges) only. If the negative edge occurs while the interrupt mask bit is set, the
interrupt signal will be latched, and interrupt will occur as soon as the interrupt mask bit is
cleared. The latch will be cleared by RESET or cleared automatically during fetch of the
EXTERNAL INTERRUPT vectors. Therefore, one (and only one) external interrupt edge
could be latched while the interrupt mask bit is set. If the INHIRQ bit in the MFT register is
set, no IRQ interrupt can be generated.
4.2
Reset Interrupt Sequence
The RESET function is not in the strictest sense an interrupt; however, it is acted upon in a
similar manner. A low level input on the RESET pin or an internally generated reset signal
causes the program to vector to its starting address which is specified by the contents of
$3FFE and $3FFF. The I-bit in the condition code register is also set. The MCU is
configured to a known state during this type of reset as described in
SECTION 5
.
4.3
Software Interrupt (SWI)
The SWI is an executable instruction and a non-maskable interrupt since it is executed
regardless of the state of the I-bit in the CCR. If the I-bit is zero (interrupts enabled), the
SWI instruction executes after interrupts which were pending before the SWI was fetched,
or before interrupts generated after the SWI was fetched. The interrupt service routine
address is specified by the contents of $3FFC and $3FFD.
4.4
Hardware Interrupts
All hardware interrupts except RESET are maskable by the I-bit in the CCR. If the I-bit is
set, all hardware interrupts (internal and external) are disabled. Clearing the I-bit enables
the hardware interrupts. There are four types of hardware interrupts which are explained in
the following sections.
4.4.1
External Interrupt (IRQ)
If the IRQ option is edge and level sensitive triggering (IRQN=0), a low level at the IRQ pin
and a cleared interrupt mask bit of the condition code register will cause an EXTERNAL
INTERRUPT to occur. If the MCU has finished with the interrupt service routine, but the IRQ
pin is still low, the EXTERNAL INTERRUPT will start again. In fact, the MCU will keep on
servicing the EXTERNAL INTERRUPT as long as the IRQ pin is low. If the IRQ pin goes
low for a while and resumes to high (a negative pulse) before the interrupt mask bit is
cleared, the MCU will not recognize there was an interrupt request, and no interrupt will
occur after the interrupt mask bit is cleared.
If the IRQ option is negative edge sensitive triggering (IRQN=1), a negative edge occurs at
the IRQ pin and a cleared interrupt mask bit of the condition code register will cause an
EXTERNAL INTERRUPT to occur. If the MCU has finished with the interrupt service
The service routine address is specified by the contents of $3FFA and $3FFB.
Figure 4-2
shows the two methods for the interrupt line (IRQ) to be recognized by the processor. The
first method is single pulses on the interrupt line spaced far apart enough to be serviced.
The minimum time between pulses is a function of the number of cycles required to execute
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| 68HC05BD7 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:SPECIFICATION REV 2.0 (General Release) |
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| 68HC05C4AFB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| 68HC05C4AFN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
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