- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄369230 > 68HC705PL4 (Motorola, Inc.) 8-Bit Microcontroller Units (MCU).(8位微控制器) PDF資料下載
參數(shù)資料
| 型號(hào)： | 68HC705PL4 |
| 廠(chǎng)商： | Motorola, Inc. |
| 英文描述： | 8-Bit Microcontroller Units (MCU).(8位微控制器) |
| 中文描述： | 8位微控制器單元（MCU）。（8位微控制器） |
| 文件頁(yè)數(shù)： | 36/98頁(yè) |
| 文件大小： | 1019K |
| 代理商： | 68HC705PL4 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)當(dāng)前第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)
GENERAL RELEASE SPECIFICATION
April 30, 1998
MOTOROLA
5-4
RESETS
MC68HC05PL4
REV 2.0
Use the following formula to calculate the COP time-out period:
COP Time-out Period = (prescaler x 256 x 8)
÷
f
BUS
where prescaler is the Timer8 prescaler value
The clock input to the watchdog system is derived from the output of the Timer8,
therefore a reset or preset of Timer8 may affect the COP watchdog time-out
period.
The COP Watchdog reset will assert the pulldown device to pull the RESET pin
low for 3-4 cycles of the internal bus clock.
The COP reset can be enable or disable by the COPON bit in MISCR. The MISCR
is in
Figure 5-5
.
COPON — COP On
Since the COP Watchdog system is derived from the 8-bit Timer system, the
T8EN bit in the Timer8 Control and Status register (bit3 of $0D) must be set for
COPON bit to have any affect.
COPON can be set to enable the COP watchdog system. Once set, the watch-
dog system cannot be disabled other than by a power-on reset or external
reset. After a reset the COPON bit is cleared and the COP watchdog system is
disabled.
1 =
COP Watchdog enabled.
0 =
COP Watchdog disabled.
NOTE
The COP Watchdog system is not designed to operate in STOP mode, therefore it
should be disabled before entering STOP mode by clearing the COPON bit.
Entering STOP mode with COP watchdog enabled will cause an internal reset of
the MCU.
5.3.3 Illegal Address Reset
An opcode fetch from an address that is not in the ROM (locations $0E00–$1DFF
and $1FF0-$1FFF) or the RAM (locations $0020–$011F) generates an illegal
address reset. The illegal address reset will assert the pulldown device to pull the
RESET pin low for 3-4 cycles of the internal bus clock.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
MICSR
$001C
RESET
R
W
IRQEN
IRQS
TCMPEN
TCAPEN
LED
COPON
POR
0
0
0
0
0
0
0
0
Figure 5-5. Miscellaneous Control and Status Register (MICSR)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 68HC705PL4B | 8-Bit Microcontroller Units (MCU).(8位微控制器) |
| 68HC908JB8FS | Freescale Semiconductor, Inc. |
| 69190-405 | 50/100M SOT-23 CMOS RF LDO REGULATORS |
| 6A20G | CURRENT 6.0 Amperes VOLTAGE 50 to 1000 Volts |
| 6A40G | CURRENT 6.0 Amperes VOLTAGE 50 to 1000 Volts |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 68HC705PL4B | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:Industry standard 8-bit M68HC05 CPU core |
| 68HC705RC17 | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:Genneral Release Specification |
| 68HC705SB7 | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:SPECIFICATION (General Release) |
| 68HC705SJ7 | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:General Release Specification |
| 68HC705SP7 | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:General Release Specification |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。