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| 型號(hào)： | MC92600 |
| 廠商： | Motorola, Inc. |
| 英文描述： | High-speed, Full-duplex, Serial Data Interface(高速全雙工串行數(shù)據(jù)接口) |
| 中文描述： | 高速，全雙工，串行數(shù)據(jù)接口（高速全雙工串行數(shù)據(jù)接口） |
| 文件頁(yè)數(shù)： | 32/82頁(yè) |
| 文件大小： | 1056K |
| 代理商： | MC92600 |
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3-10
MC92600 WarpLink Quad Users Manual
Device Operations
overrun is imminent. However, the idle is dropped only if add/delete idle (ADI) mode is
enabled by setting ADIE high. When enabled, idle patterns are dropped to maintain
synchronization. If sufTcient idle patterns are not available to drop, receiver overrun may
occur. When overrun occurs, the overrun/underrun error is reported as described in
Section 3.7, òReceiver Interface Error Codes,ó for one byte clock period. Overrun error is
also reported if ADI mode is disabled and overrun occurs, even if idles are available to drop.
A sufTcient number of idles must be transmitted to guard against overrun. The frequency
of idles can be computed based upon the maximum frequency offset between transmitter
and receiver in the system. The number of bytes (characters) that can be transmitted
between idles is:
(10
6
/ N) - 1 bytes
where:
N is the frequency offset in ppm.
In an underrun situation, a byte of data needs to be added to maintain synchronization
between the clock domains. The receiver interface adds an idle byte when underrun is
imminent. However, the idle is added only if add/delete idle (ADI) mode is enabled by
asserting ADIE. If ADI mode is disabled and underrun occurs, the overrun/underrun error
is reported as described in Section 3.7 for one byte clock period.
Data is timed to the rising edge of the reference clock signal except in double data rate mode
where data is timed to the rising and falling edges of the reference clock.
3.5 Device Operations
The WarpLink receiver is comprised of several devices and operations that are described in
the following sections.
3.5.1 Receiver Input AmpliTer
The input ampliTer connects directly to the link input pads RLINK_n_P and RLINK_n_N.
It is a differential ampliTer with an integrated analog multiplexer for loop-back testing.
Link termination resistors are integrated with the ampliTer. The termination resistance is
programmable to be 100
W
differential or 150
W
differential through the MEDIA signal.
Termination resistance is 100
W
when MEDIA is low and 150
W
when MEDIA is high.
The input ampliTer facilitates a loop-back path for production and in-system testing. When
the WarpLink Quad is in loop-back mode (LBE is high), the input ampliTer selects the
loop-back differential input signals and ignores the state on the RLINK_n_P and
RLINK_n_N signals. This allows in-system loop-back BIST independent of the current
input state. See Chapter 5 for more information on test modes.
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