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| 型號(hào)： | MC92600 |
| 廠商： | Motorola, Inc. |
| 英文描述： | High-speed, Full-duplex, Serial Data Interface(高速全雙工串行數(shù)據(jù)接口) |
| 中文描述： | 高速，全雙工，串行數(shù)據(jù)接口（高速全雙工串行數(shù)據(jù)接口） |
| 文件頁(yè)數(shù)： | 44/82頁(yè) |
| 文件大小： | 1056K |
| 代理商： | MC92600 |
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5-2
MC92600 WarpLink Quad Users Manual
BIST Sequence System Test Mode
5.2 BIST Sequence System Test Mode
The WarpLink Quads transmitter has an integrated, 23rd order, pseudo-noise (PN) pattern
generator. Stimulus from this generator may be used for internal built-in self testing (BIST).
The receiver has a 23rd order signature analyzer that is synchronized to the incoming PN
stream and may be used to count character mismatch errors relative to the internal PN
reference pattern.
To properly use the BIST sequence system test mode, the system must provide the proper
stimulus in a special sequence. The sequence of steps to run a BIST test is as follows:
1. Select the reference clock frequency at which you wish to run the BIST test. See
Table 3-5 , "Legal Reference Clock Frequency Rangesó for pin settings for HSE and
DDRE modes.
2. Enter test mode by setting the test mode inputs as described in Table 5-1.
3. Transmit two 4/1 word synchronization event sequences.
4. Transmit to the receiver an 8B10B encoded PN sequence as described above.
The transmitter will automatically go through steps 3 and 4 upon entering this test mode.
Upon completion of testing, the transceiver will need to be re-synchronized before normal
operation can resume.
This implementation of the 23-bit PN generator and analyzer uses the polynomial:
f = 1 + x
5
+ x
23
The total mismatch error count is reset to zero when BIST mode is entered. The count is
updated continuously while in BIST mode. The value of the count is presented on the
receiver interface signals: RECV_n_7 through RECV_n_0, making up the eight-bit error
count, ordered bits 7 through 0, respectively. The value of the count is sticky in that the
count will not wrap to zero upon overow, but rather stays at the maximum count value
(11111111).
The RECV_n_ERR, RECV_n_K and RECV_n_IDLE have special meaning during this
test mode. They report the status of the receiver and PN analysis logic. Table 5-2 , "BIST
Error Codesó describes the BIST error codes and their meaning..
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