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參數資料
| 型號： | 68HC05BD7 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 8-Bit Microcontroller Units (MCU).(8位微控制器) |
| 中文描述： | 8位微控制器單元（MCU）。（8位微控制器） |
| 文件頁數： | 31/85頁 |
| 文件大小： | 302K |
| 代理商： | 68HC05BD7 |
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SECTION 4: INTERRUPTS
MOTOROLA
Page 21
MC68HC05BD7 Rev. 2.0
GENERAL RELEASE SPECIFICATION
N/A
N/A
N/A
SECTION 4
INTERRUPTS
4.1
CPU Interrupt Processing
Interrupts cause the processor to save register contents on the stack and to set the interrupt
mask (I-bit) to prevent additional interrupts. Unlike RESET, hardware interrupts do not
cause the current instruction execution to be halted, but are considered pending until the
current instruction is complete.
If interrupts are not masked (I-bit in the CCR is cleared) and the corresponding interrupt
enable bit is set the processor will proceed with interrupt processing. Otherwise, the next
instruction is fetched and executed. If an interrupt occurs the processor completes the
current instruction, then stacks the current CPU register states, sets the I-bit to inhibit
further interrupts, and finally checks the pending hardware interrupts. If more than one
interrupt is pending following the stacking operation, the interrupt with the highest vector
location shown in
Table 4-1
will be serviced first. The SWI is executed the same as any
other instruction, regardless of the I-bit state.
When an interrupt is to be processed the CPU fetches the address of the appropriate
interrupt software service routine from the vector table at locations $3FF0 thru $3FFF as
defined in
Table 4-1
.
Table 4-1: Vector Address for Interrupts and Reset
An RTI instruction is used to signify when the interrupt software service routine is
completed. The RTI instruction causes the register contents to be recovered from the stack
and normal processing to resume at the next instruction that was to be executed when the
interrupt took place.
Figure 4-1
shows the sequence of events that occur during interrupt
processing.
Register
N/A
N/A
N/A
SPCSR
DMCR
DSR
MFTCSR
Flag
N/A
N/A
N/A
VSIF
TXIF
RXIF
ALIF
NAKIF
SCLIF
TOF
RTIF
N/A
Interrupts
Reset
Software
External Interrupt
VSINT
DDC12AB interrupt
Timer Overflow
Real Time Interrupt
N/A
CPU Int
RESET
SWI
IRQ
SP
DDC12AB
MFT
N/A
N/A
Vector Adds.
$3FFE-$3FFF
$3FFC-$3FFD
$3FFA-$3FFB
$3FF8-$3FF9
$3FF6-$3FF7
$3FF4-$3FF5
$3FF2-$3FF3
$3FF0-$3FF1
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