- 您現在的位置：買賣IC網 > PDF目錄369230 > 68HC05BD7 (Motorola, Inc.) 8-Bit Microcontroller Units (MCU).(8位微控制器) PDF資料下載
參數資料
| 型號： | 68HC05BD7 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 8-Bit Microcontroller Units (MCU).(8位微控制器) |
| 中文描述： | 8位微控制器單元（MCU）。（8位微控制器） |
| 文件頁數： | 68/85頁 |
| 文件大小： | 302K |
| 代理商： | 68HC05BD7 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁當前第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁
MOTOROLA
Page 58
SECTION 11: MULTI-FUNCTION TIMER
GENERAL RELEASE SPECIFICATION
MC68HC05BD7 Rev. 2.0
PRELMNARY
count of the divide-by-64 counter is hence 63 rather than 64.
RT1, RT0 should only be changed right after COP timer has
been reset; otherwise, unpredictable result will occur.
$FF to $00. A CPU interrupt request will be generated if
TOFIE is set. TOF is a clearable, read-only status bit. Clearing
the TOF is done by writing a ’0’ to TOF.
Real Time Interrupt Flag indicates if the output of the RTI
circuit goes active. The clock frequency that drives the RTI
circuit is E/2,048, giving a maximum interrupt period of 1.024
milliseconds at a bus rate of 2 MHz. A CPU interrupt request
will be generated if RTIE is set. RTIF is a clearable, read-only
status bit. Clearing the RTIF is done by writing a ’0’ to RTIF.
When Timer Over Flow Interrupt Enable (TOFIE) bit is set, the
TOF flag is enabled to generate an interrupt request to the
generating an interrupt request.
When Real Time Interrupt Enable (RTIE) is set, the RTIF flag
is enabled to generate an interrupt request to the CPU. When
RTIE is cleared, the RTIF flag is prevented from generating an
interrupt request.
0 = Both level and edge triggering are detected for external
interrupt (IRQ).
1 = Only edge triggering is detected for external interrupt.
The INHibit IRQ bit will inhibit the external interrupt input.
When it is set, no active falling edge or low period will be
recognized as interrupt request. It is possible for a low state
input on the IRQ pin to be seen as a falling edge event when
the INHIRQ bit changes from one to zero, see
Figure 4-2
for
reference. Reset clears this bit.
These two bits are used to define real time interrupt rate as
well as COP reset rate as tabulated in
Table 11-1
. Reset sets
these two bits for the slowest watchdog reset rate. Note that
the minimal COP reset period is determined by dividing the
COP master clock, which is the real time interrupt clock, by
63(63=64-1). The reason is that COP reset operation is
asynchronous to COP master clock edge. Therefore it is
possible that right after COP reset operation, a COP master
RTIF
bit 6
TOFIE
bit 5
RTIE
bit 4
IRQN
bit 3
INHIRQ
bit 2
RT1-0
bit 1,0
相關PDF資料 |
PDF描述 |
|---|---|
| 68HC705BD7 | 8-Bit Microcontroller Units (MCU).(8位微控制器) |
| 68HC05J5A | 8-Bit Microcontroller Units (MCU).(8位微控制器) |
| 68HC705J5A | 8-Bit Microcontroller Units (MCU).(8位微控制器) |
| 68HRC05J5A | 8-Bit Microcontroller Units (MCU).(8位微控制器) |
| 68HRC705J5A | 8-Bit Microcontroller Units (MCU).(8位微控制器) |
相關代理商/技術參數 |
參數描述 |
|---|---|
| 68HC05C0FN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| 68HC05C0P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| 68HC05C4AFB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| 68HC05C4AFN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| 68HC05C4AP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
發布緊急采購，3分鐘左右您將得到回復。