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參數(shù)資料
| 型號(hào)： | 68HC05BD7 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 8-Bit Microcontroller Units (MCU).(8位微控制器) |
| 中文描述： | 8位微控制器單元（MCU）。（8位微控制器） |
| 文件頁(yè)數(shù)： | 72/85頁(yè) |
| 文件大小： | 302K |
| 代理商： | 68HC05BD7 |
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MOTOROLA
Page 62
SECTION 12: A/D CONVERTER
GENERAL RELEASE SPECIFICATION
MC68HC05BD7 Rev. 2.0
CHSL1:CHSL0 - Channel select bits
These two bit will select one of the four ADC input channels
as analog input source. Following table shows its
configuration.
12.3
Registers
12.3.1
ADC Control/status Register
This read/write register, located at address $14, contains six control bits and one status bit.
RESULT - Comparator Status Bit (Read Only)
When set, D/A output
≥
ANALOG IN.
When clear, D/A output
≥
ANALOG IN.
AD5:0 - A/D Digital Result
These bits are written by the user to perform successive
approximations in software. When a value causes the
RESULT bit to change state from the value immediately
before or after it, AD5:0 are considered to be the digital
equivalent of the analog input. Note that when AD5:0 are all
1’s, ADC is virtually turned off to minimize power
consumption.
12.3.2
ADC Channel Register
The ADC Channel Register, located at address $15 contains only two bits.
CHSL1:CHSL0 = 0 : 0 ==> ADC0
CHSL1:CHSL0 = 0 : 1 ==> ADC1
CHSL1:CHSL0 = 1 : 0 ==> ADC2
CHSL1:CHSL0 = 1 : 1 ==> ADC3
0
7
0
0
0
0
0
0
0
6
5
4
3
2
1
0
W
R
ADCSR
$0014
reset
RESULT
AD5
AD4
AD3
AD2
AD1
AD0
0
7
0
0
0
0
0
0
0
6
5
4
3
2
1
0
W
R
ADCCR
$0015
reset
CHSL1
CHSL0
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